//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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riffa_chnl_rx_fsm
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riffa_chnl_rx_fsm
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(
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(
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input rx,
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input rx,
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input rx_data_valid,
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input rx_data_valid,
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input rx_ready,
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input rx_ready,
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output rx_ack,
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output rx_ack,
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output rx_done,
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output rx_done,
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input reset,
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input reset,
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input clk
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input clk
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// state machine binary definitions
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// state machine binary definitions
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enum reg [4:0]
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enum reg [4:0]
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{
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{
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IDLE = 5'b0_0001,
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IDLE = 5'b0_0001,
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ACK = 5'b0_0010,
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ACK = 5'b0_0010,
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RX = 5'b0_0100,
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RX = 5'b0_0100,
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PENDING = 5'b0_1000,
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PENDING = 5'b0_1000,
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ERROR = 5'b1_0000
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ERROR = 5'b1_0000
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} state, next_state;
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} state, next_state;
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//---------------------------------------------------
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//---------------------------------------------------
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// state machine flop
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// state machine flop
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if(reset)
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if(reset)
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state <= IDLE;
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state <= IDLE;
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else
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else
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state <= next_state;
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state <= next_state;
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//---------------------------------------------------
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//---------------------------------------------------
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// state machine
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// state machine
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always_comb
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always_comb
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case(state)
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case(state)
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IDLE: if(rx)
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IDLE: if(rx)
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next_state <= ACK;
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next_state <= ACK;
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else
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else
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next_state <= IDLE;
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next_state <= IDLE;
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// ACK: next_state <= RX;
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ACK: if(rx_ready)
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ACK: if(rx_ready)
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next_state <= RX;
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next_state <= RX;
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else
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else
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next_state <= ACK;
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next_state <= ACK;
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RX: if(rx)
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RX: if(rx)
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next_state <= RX;
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next_state <= RX;
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else if(rx_data_valid)
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else if(rx_data_valid)
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next_state <= PENDING;
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next_state <= PENDING;
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else
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else
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next_state <= IDLE;
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next_state <= IDLE;
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PENDING: if(rx_data_valid)
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PENDING: if(rx_data_valid)
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next_state <= PENDING;
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next_state <= PENDING;
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else
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else
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next_state <= IDLE;
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next_state <= IDLE;
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ERROR: next_state <= IDLE;
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ERROR: next_state <= IDLE;
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default: next_state <= ERROR;
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default: next_state <= ERROR;
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endcase
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endcase
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign rx_ack = (state == ACK);
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assign rx_ack = (state == ACK);
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assign rx_done = (state != IDLE) & (next_state == IDLE);
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assign rx_done = (state != IDLE) & (next_state == IDLE);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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