| Line 54... |
Line 54... |
output [(C_NUM_CHNL*SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
|
output [(C_NUM_CHNL*SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
|
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
|
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
|
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
|
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
|
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN, // Channel write data has been received
|
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN, // Channel write data has been received
|
|
|
riffa_chnl_if chnl_in[C_NUM_CHNL]
|
riffa_chnl_if chnl_bus[C_NUM_CHNL]
|
);
|
);
|
|
|
// --------------------------------------------------------------------
|
// --------------------------------------------------------------------
|
//
|
//
|
genvar i;
|
genvar i;
|
generate
|
generate
|
for (i = 0; i < C_NUM_CHNL; i = i + 1)
|
for (i = 0; i < C_NUM_CHNL; i = i + 1)
|
begin : channels
|
begin : channels
|
assign CHNL_RX_CLK[i] = chnl_in[i].rx_clk;
|
assign CHNL_RX_CLK[i] = chnl_bus[i].rx_clk;
|
assign chnl_in[i].rx = CHNL_RX[i];
|
assign chnl_bus[i].rx = CHNL_RX[i];
|
assign CHNL_RX_ACK[i] = chnl_in[i].rx_ack;
|
assign CHNL_RX_ACK[i] = chnl_bus[i].rx_ack;
|
assign chnl_in[i].rx_last = CHNL_RX_LAST[i];
|
assign chnl_bus[i].rx_last = CHNL_RX_LAST[i];
|
assign chnl_in[i].rx_len = CHNL_RX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W];
|
assign chnl_bus[i].rx_len = CHNL_RX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W];
|
assign chnl_in[i].rx_off = CHNL_RX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W];
|
assign chnl_bus[i].rx_off = CHNL_RX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W];
|
assign chnl_in[i].rx_data = CHNL_RX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH];
|
assign chnl_bus[i].rx_data = CHNL_RX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH];
|
assign chnl_in[i].rx_data_valid = CHNL_RX_DATA_VALID[i];
|
assign chnl_bus[i].rx_data_valid = CHNL_RX_DATA_VALID[i];
|
assign CHNL_RX_DATA_REN[i] = chnl_in[i].rx_data_ren;
|
assign CHNL_RX_DATA_REN[i] = chnl_bus[i].rx_data_ren;
|
|
|
assign CHNL_TX_CLK[i] = chnl_in[i].tx_clk;
|
assign CHNL_TX_CLK[i] = chnl_bus[i].tx_clk;
|
assign CHNL_TX[i] = chnl_in[i].tx;
|
assign CHNL_TX[i] = chnl_bus[i].tx;
|
assign chnl_in[i].tx_ack = CHNL_TX_ACK[i];
|
assign chnl_bus[i].tx_ack = CHNL_TX_ACK[i];
|
assign CHNL_TX_LAST[i] = chnl_in[i].tx_last;
|
assign CHNL_TX_LAST[i] = chnl_bus[i].tx_last;
|
assign CHNL_TX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W] = chnl_in[i].tx_len;
|
assign CHNL_TX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W] = chnl_bus[i].tx_len;
|
assign CHNL_TX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W] = chnl_in[i].tx_off;
|
assign CHNL_TX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W] = chnl_bus[i].tx_off;
|
assign CHNL_TX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH] = chnl_in[i].tx_data;
|
assign CHNL_TX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH] = chnl_bus[i].tx_data;
|
assign CHNL_TX_DATA_VALID[i] = chnl_in[i].tx_data_valid;
|
assign CHNL_TX_DATA_VALID[i] = chnl_bus[i].tx_data_valid;
|
assign chnl_in[i].tx_data_ren = CHNL_TX_DATA_REN[i];
|
assign chnl_bus[i].tx_data_ren = CHNL_TX_DATA_REN[i];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
// // --------------------------------------------------------------------
|
// // --------------------------------------------------------------------
|
