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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_register_file.sv] - Diff between revs 34 and 35

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module
module
  riffa_register_file
  riffa_register_file
  #(
  #(
    A, //  address bus width
 
    N, //  data bus width in bytes
    N, //  data bus width in bytes
    MW = 3 //  mux select width
    B // number of register banks
  )
  )
  (
  (
    riffa_chnl_if chnl_in,
    riffa_chnl_if chnl_in,
    riffa_register_if r_if,
    riffa_register_if r_if,
    input clk,  // must be same clock domain as rx_clk & tx_clk
    input clk,  // must be same clock domain as rx_clk & tx_clk
    input reset // must be same clock domain as rx_clk & tx_clk
    input reset // must be same clock domain as rx_clk & tx_clk
  );
  );
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
// synthesis translate_off
    initial
    initial
 
    begin
      a_data_bus_mod: assert(N % 4 == 0) else $fatal;
      a_data_bus_mod: assert(N % 4 == 0) else $fatal;
 
      a_data_bus_power_of_2: assert((N != 0) & ((N & (N - 1)) == 0)) else $fatal;
 
    end
// synthesis translate_on
// synthesis translate_on
// --------------------------------------------------------------------
// --------------------------------------------------------------------
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  localparam RW = (N/4); // width of the bus in 32 bit words
  localparam RW = (N/4); // width of the bus in 32 bit words
  localparam MI = 2 ** MW; //  mux inputs
  localparam RC = RW * B; // number of available registers
  localparam LB = $clog2(RW);
 
  localparam UB = LB + MW;
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
 
  wire rx_ready = ~reset;
  wire rx_done;
  wire rx_done;
  wire [31:0] rx_index;
  wire [30:0] rx_index;
  wire rx_last;
  wire rx_last;
  wire [31:0] rx_len;
  wire [31:0] rx_len;
  wire [30:0] rx_off;
  wire [30:0] rx_off; // offset ignored, always start from offset 0
  wire rx_data_ren;
  // wire rx_data_ren;
  wire rd_empty;
  wire rd_empty;
  wire [(8*N)-1:0] rd_data;
  wire [(8*N)-1:0] rd_data;
  wire rd_en;
  wire rd_en;
  riffa_chn_rx #(.N(N))
  riffa_chn_rx #(.N(N))
    riffa_chn_rx_i(.*);
    riffa_chn_rx_i(.chnl_bus(chnl_in), .*);
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  wire register_select [MI-1:0];
  wire register_select [RC-1:0];
  genvar j;
  genvar j, k;
 
 
  generate
  generate
    for(j = 0; j < MI; j = j + 1)
    for(j = 0; j < B; j = j + 1)
    begin: decoder_gen
    begin: register_j_gen
      assign register_select[j] = (rx_index[UB:LB] == j) & (rx_index[31:UB] == 0) ? 1 : 0;
      for(k = 0; k < RW; k = k + 1)
 
      begin: register_k_gen
 
        assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
 
 
      always_ff @(posedge clk)
        always_ff @(posedge clk)
        if(reset)
        if(reset)
          r_if.register_out[j] <= 0;
            r_if.register_out[(j*RW) + k] <= 0;
        else if(rd_en & register_select[j])
          else if(rd_en & register_select[(j*RW) + k])
          r_if.register_out[j] <= rd_data;
            r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
 
      end
    end
    end
  endgenerate
  endgenerate
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  assign chnl_in.rx_data_ren = rx_data_ren;
  // assign chnl_in.rx_data_ren = rx_data_ren;
  assign rd_en = ~rd_empty;
  assign rd_en = ~rd_empty;
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  wire tx_ready = 1;
  wire tx_ready = 1;
  wire tx_last = 1;
  wire tx_last = 1;
  wire [31:0] tx_len = RW*MI;
  wire acked;
 
  wire [31:0] tx_len = RC;
  wire [30:0] tx_off = 0;
  wire [30:0] tx_off = 0;
  wire [31:0] tx_index;
  wire [30:0] tx_index;
  wire tx_done = (tx_index >= chnl_in.tx_len - RW);
  wire tx_done = (tx_index >= chnl_in.tx_len - RW);
  riffa_chn_tx #(.N(N))
  riffa_chn_tx #(.N(N))
    riffa_chn_tx_i(.*);
    riffa_chn_tx_i(.*);
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  recursive_mux #(.A(MW), .W(N*8))
  wire [(N*8)-1:0] data_in [(2 ** $clog2(B))-1:0];
 
 
 
  generate
 
    for(j = 0; j < B; j = j + 1)
 
    begin: data_in_j_gen
 
      for(k = 0; k < RW; k = k + 1)
 
      begin: data_in_k_gen
 
        assign data_in[j][k*32 +: 32] = r_if.register_out[(j*RW) + k];
 
      end
 
    end
 
  endgenerate
 
 
 
 
 
  // --------------------------------------------------------------------
 
  //
 
  recursive_mux #(.A($clog2(B)), .W(N*8))
    recursive_mux_i
    recursive_mux_i
    (
    (
      .select(tx_index[UB:LB]),
      .select(tx_index[$clog2(B) + $clog2(RW) - 1:$clog2(RW)]),
      .data_in(r_if.register_in),
      .data_out(chnl_in.tx_data),
      .data_out(chnl_in.tx_data)
      .*
    );
    );
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  assign chnl_in.rx_clk = clk;
  assign chnl_in.rx_clk = clk;
  assign chnl_in.tx_clk = clk;
  assign chnl_in.tx_clk = clk;
  assign chnl_in.rx_reset = reset;
  assign chnl_in.rx_reset = reset;
  assign chnl_in.tx_reset = reset;
  assign chnl_in.tx_reset = reset;
  assign chnl_in.tx_last = 1;
  assign chnl_in.tx_last = 1;
  assign chnl_in.tx_len = RW*MI;
  assign chnl_in.tx_len = RC;
  assign chnl_in.tx_off = 0;
  assign chnl_in.tx_off = 0;
  assign chnl_in.tx_data_valid = 1;
  assign chnl_in.tx_data_valid = acked;
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
//
endmodule
endmodule
 
 

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