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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_register_file.sv] - Diff between revs 35 and 37
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| Rev 35 |
Rev 37 |
| Line 81... |
Line 81... |
for(j = 0; j < B; j = j + 1)
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for(j = 0; j < B; j = j + 1)
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begin: register_j_gen
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begin: register_j_gen
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for(k = 0; k < RW; k = k + 1)
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for(k = 0; k < RW; k = k + 1)
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begin: register_k_gen
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begin: register_k_gen
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assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
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assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
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assign r_if.wr_en[(j*RW) + k] = rd_en & register_select[(j*RW) + k];
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if(reset)
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if(reset)
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r_if.register_out[(j*RW) + k] <= 0;
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r_if.register_out[(j*RW) + k] <= 0;
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else if(rd_en & register_select[(j*RW) + k])
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else if(r_if.wr_en[(j*RW) + k])
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r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
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r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
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end
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end
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end
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end
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endgenerate
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endgenerate
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| Line 100... |
Line 101... |
assign rd_en = ~rd_empty;
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assign rd_en = ~rd_empty;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire tx_ready = 1;
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// write to register[0][0] to enable reading
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wire tx_ready = r_if.wr_en[0] & rd_data[0];
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wire tx_last = 1;
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wire tx_last = 1;
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wire acked;
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wire acked;
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wire [31:0] tx_len = RC;
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wire [31:0] tx_len = RC;
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wire [30:0] tx_off = 0;
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wire [30:0] tx_off = 0;
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wire [30:0] tx_index;
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wire [30:0] tx_index;
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