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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_register_file.sv] - Diff between revs 35 and 37

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Rev 35 Rev 37
Line 81... Line 81...
    for(j = 0; j < B; j = j + 1)
    for(j = 0; j < B; j = j + 1)
    begin: register_j_gen
    begin: register_j_gen
      for(k = 0; k < RW; k = k + 1)
      for(k = 0; k < RW; k = k + 1)
      begin: register_k_gen
      begin: register_k_gen
        assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
        assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
 
        assign r_if.wr_en[(j*RW) + k]       = rd_en & register_select[(j*RW) + k];
 
 
        always_ff @(posedge clk)
        always_ff @(posedge clk)
          if(reset)
          if(reset)
            r_if.register_out[(j*RW) + k] <= 0;
            r_if.register_out[(j*RW) + k] <= 0;
          else if(rd_en & register_select[(j*RW) + k])
          else if(r_if.wr_en[(j*RW) + k])
            r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
            r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
      end
      end
    end
    end
  endgenerate
  endgenerate
 
 
Line 100... Line 101...
  assign rd_en = ~rd_empty;
  assign rd_en = ~rd_empty;
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  wire tx_ready = 1;
  // write to register[0][0] to enable reading
 
  wire tx_ready = r_if.wr_en[0] & rd_data[0];
  wire tx_last = 1;
  wire tx_last = 1;
  wire acked;
  wire acked;
  wire [31:0] tx_len = RC;
  wire [31:0] tx_len = RC;
  wire [30:0] tx_off = 0;
  wire [30:0] tx_off = 0;
  wire [30:0] tx_index;
  wire [30:0] tx_index;

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