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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_if.sv] - Diff between revs 23 and 29

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Rev 23 Rev 29
Line 27... Line 27...
 
 
 
 
interface
interface
  axi4_if
  axi4_if
  #(
  #(
    DATA_WIDTH = 64
    A = 32, // address bus width
 
    N = 8,  // data bus width in bytes
 
    I = 1   // ID width
  )
  )
  (
  (
    input                   aresetn,
    input                   aresetn,
    input                   aclk
    input                   aclk
  );
  );
 
 
    wire                    arready;
  logic [(A-1):0]    araddr;
    wire                    arregion;
  logic [1:0]        arburst;
    wire                    awready;
  logic [3:0]        arcache;
    wire                    awregion;
  logic [(I-1):0]    arid;
    wire                    bvalid;
  logic [7:0]        arlen;
    wire                    rlast;
  logic              arlock;
    wire                    rvalid;
  logic [2:0]        arprot;
    wire                    wready;
  logic [3:0]        arqos;
    wire [1:0]              bresp;
  logic              arready;
    wire [1:0]              rresp;
  logic [3:0]        arregion;
    wire [5:0]              bid;
  logic [2:0]        arsize;
    wire [5:0]              rid;
  logic              arvalid;
    wire [DATA_WIDTH-1:0]   rdata;
  logic [(A-1):0]    awaddr;
    wire [7:0]              rcount;
  logic [1:0]        awburst;
    wire [7:0]              wcount;
  logic [3:0]        awcache;
    wire [2:0]              racount;
  logic [(I-1):0]    awid;
    wire [5:0]              wacount;
  logic [7:0]        awlen;
    wire                    arvalid;
  logic              awlock;
    wire                    awvalid;
  logic [2:0]        awprot;
    wire                    bready;
  logic [3:0]        awqos;
    wire                    rready;
  logic              awready;
    wire                    wlast;
  logic [3:0]        awregion;
    wire                    wvalid;
  logic [2:0]        awsize;
    wire [1:0]              arburst;
  logic              awvalid;
    wire [1:0]              arlock;
  logic [(I-1):0]    bid;
    wire [2:0]              arsize;
  logic              bready;
    wire [1:0]              awburst;
  logic [1:0]        bresp;
    wire [1:0]              awlock;
  logic              bvalid;
    wire [2:0]              awsize;
  logic [(8*N)-1:0]  rdata;
    wire [2:0]              arprot;
  logic [(I-1):0]    rid;
    wire [2:0]              awprot;
  logic              rlast;
    wire [31:0]             araddr;
  logic              rready;
    wire [31:0]             awaddr;
  logic [1:0]        rresp;
    wire [3:0]              arcache;
  logic              rvalid;
    wire [7:0]              arlen;
  logic [(8*N)-1:0]  wdata;
    wire [3:0]              arqos;
  logic [(I-1):0]    wid;
    wire [3:0]              awcache;
  logic              wlast;
    wire [3:0]              awlen;
  logic              wready;
    wire [3:0]              awqos;
  logic [N-1:0]      wstrb;
    wire [5:0]              arid;
  logic              wvalid;
    wire [5:0]              awid;
 
    wire [5:0]              wid;
 
    wire [DATA_WIDTH-1:0]   wdata;
 
    wire [DATA_WIDTH/8-1:0] wstrb;
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  modport
 
    master
 
    (
 
      output  arid,
 
      output  araddr,
 
      output  arburst,
 
      output  arcache,
 
      output  arlen,
 
      output  arlock,
 
      output  arprot,
 
      output  arqos,
 
      input   arready,
 
      output  arregion,
 
      output  arsize,
 
      output  arvalid,
 
      output  awaddr,
 
      output  awburst,
 
      output  awcache,
 
      output  awlen,
 
      output  awlock,
 
      output  awprot,
 
      output  awqos,
 
      input   awready,
 
      output  awregion,
 
      output  awsize,
 
      output  awvalid,
 
      output  bready,
 
      input   bresp,
 
      input   bvalid,
 
      input   rdata,
 
      input   rlast,
 
      output  rready,
 
      input   rresp,
 
      input   rvalid,
 
      output  wdata,
 
      output  wlast,
 
      input   wready,
 
      output  wstrb,
 
      output  wvalid,
 
      input   aresetn,
 
      input   aclk
 
    );
 
 
 
  modport
 
    slave
 
    (
 
      input   arid,
 
      input   araddr,
 
      input   arburst,
 
      input   arcache,
 
      input   arlen,
 
      input   arlock,
 
      input   arprot,
 
      input   arqos,
 
      output  arready,
 
      input   arregion,
 
      input   arsize,
 
      input   arvalid,
 
      input   awaddr,
 
      input   awburst,
 
      input   awcache,
 
      input   awlen,
 
      input   awlock,
 
      input   awprot,
 
      input   awqos,
 
      output  awready,
 
      input   awregion,
 
      input   awsize,
 
      input   awvalid,
 
      input   bready,
 
      output  bresp,
 
      output  bvalid,
 
      output  rdata,
 
      output  rlast,
 
      input   rready,
 
      output  rresp,
 
      output  rvalid,
 
      input   wdata,
 
      input   wlast,
 
      output  wready,
 
      input   wstrb,
 
      input   wvalid,
 
      input   aresetn,
 
      input   aclk
 
    );
 
 
 
endinterface: axi4_if
endinterface
 
 
 
 

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