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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_m_to_read_fifos.sv] - Diff between revs 31 and 43
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| Rev 31 |
Rev 43 |
| Line 26... |
Line 26... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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axi4_m_to_read_fifos
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axi4_m_to_read_fifos
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#(
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#(
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A = 32, // address bus width
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A, // address bus width
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N = 8, // data bus width in bytes
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N, // data bus width in bytes
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I = 1, // ID width
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I, // ID width
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R_D = 32,
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R_D,
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AR_D = 2,
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AR_D,
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WATERMARK = 0,
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WATERMARK = 0,
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USE_ADVANCED_PROTOCOL = 0
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USE_ADVANCED_PROTOCOL = 0
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)
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)
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(
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(
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axi4_if axi4_m,
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axi4_if axi4_m,
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| Line 181... |
Line 181... |
wire [R_W-1:0] r_rd_data;
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wire [R_W-1:0] r_rd_data;
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wire [R_W-1:0] r_wr_data;
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wire [R_W-1:0] r_wr_data;
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assign r_wr_data =
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assign r_wr_data =
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{
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{
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axi4_m.rdata,
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axi4_m.rid,
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axi4_m.rid,
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axi4_m.rresp,
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axi4_m.rlast,
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axi4_m.rlast,
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axi4_m.rresp
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axi4_m.rdata
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};
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};
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assign
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assign
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{
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{
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axi4_read_fifo.rdata,
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axi4_read_fifo.rid,
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axi4_read_fifo.rid,
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axi4_read_fifo.rresp,
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axi4_read_fifo.rlast,
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axi4_read_fifo.rlast,
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axi4_read_fifo.rresp
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axi4_read_fifo.rdata
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} = r_rd_data;
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} = r_rd_data;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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