//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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axis_downsizer
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axis_downsizer
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#(
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#(
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N, // data bus width in bytes
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N, // data bus width in bytes
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I = 1, // TID width
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I = 1, // TID width
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D = 1, // TDEST width
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D = 1, // TDEST width
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U, // TUSER width
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U, // TUSER width
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S, // tdata size divisor
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S, // tdata size divisor
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TKEEP = 0, // set to 1 to enable, 0 to disable
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USE_TKEEP = 0, // set to 1 to enable, 0 to disable
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BYTES_PER_TUSER // bytes per tuser bit. Set to 0 for transfer based.
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BYTES_PER_TUSER // bytes per tuser bit. Set to 0 for transfer based.
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)
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)
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(
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(
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axis_if axis_in,
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axis_if axis_in,
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axis_if axis_out,
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axis_if axis_out,
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input aclk,
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input aclk,
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input aresetn
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input aresetn
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// synthesis translate_off
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// synthesis translate_off
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initial
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initial
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begin
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begin
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a_divisor: assert(S > 1) else $fatal;
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a_divisor: assert(S > 1) else $fatal;
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a_tdata_mod: assert(N % S == 0) else $fatal;
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a_tdata_mod: assert(N % S == 0) else $fatal;
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a_tstrb_unsuported: assert(USE_TSTRB == 0) else $fatal;
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a_tstrb_unsuported: assert(USE_TSTRB == 0) else $fatal;
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a_tkeep_unsuported: assert(USE_TKEEP == 0) else $fatal;
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a_tkeep_unsuported: assert(USE_TKEEP == 0) else $fatal;
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a_bytes_per_tuser: assert((BYTES_PER_TUSER == 0) | (N % BYTES_PER_TUSER == 0)) else $fatal;
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a_bytes_per_tuser: assert((BYTES_PER_TUSER == 0) | (N % BYTES_PER_TUSER == 0)) else $fatal;
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a_tuser: assert((BYTES_PER_TUSER == 0) | (U % S == 0)) else $fatal;
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a_tuser: assert((BYTES_PER_TUSER == 0) | (U % S == 0)) else $fatal;
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end
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end
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// synthesis translate_on
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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localparam M_A = $clog2(S);
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localparam M_A = $clog2(S);
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localparam M_D = 2 ** M_A;
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localparam M_D = 2 ** M_A;
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localparam M_NW = (N*8)/ S;
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localparam M_NW = (N*8)/ S;
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localparam M_UW = U / S;
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localparam M_UW = U / S;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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localparam U_OUT = (BYTES_PER_TUSER == 0) ? U : U / (N / BYTES_PER_TUSER);
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localparam U_OUT = (BYTES_PER_TUSER == 0) ? U : U / (N / BYTES_PER_TUSER);
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axis_if #(.N(N/S), .U(U_OUT)) axis_downsizer_bus(.*);
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axis_if #(.N(N/S), .U(U_OUT)) axis_downsizer_bus(.*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire almost_last_word;
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wire almost_last_word;
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//---------------------------------------------------
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//---------------------------------------------------
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// state machine binary definitions
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// state machine binary definitions
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enum reg [2:0]
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enum reg [2:0]
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{
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{
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GET_WORD_IN = 3'b001,
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GET_WORD_IN = 3'b001,
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MUX_WORD_OUT = 3'b010,
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MUX_WORD_OUT = 3'b010,
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LAST_WORD_OUT = 3'b100
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LAST_WORD_OUT = 3'b100
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} state, next_state;
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} state, next_state;
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//---------------------------------------------------
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//---------------------------------------------------
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// state machine flop
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// state machine flop
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always_ff @(posedge aclk)
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always_ff @(posedge aclk)
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if(~aresetn)
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if(~aresetn)
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state <= GET_WORD_IN;
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state <= GET_WORD_IN;
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else
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else
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state <= next_state;
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state <= next_state;
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//---------------------------------------------------
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//---------------------------------------------------
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// state machine
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// state machine
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always_comb
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always_comb
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case(state)
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case(state)
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GET_WORD_IN: if(axis_in.tvalid)
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GET_WORD_IN: if(axis_in.tvalid)
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next_state <= MUX_WORD_OUT;
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next_state <= MUX_WORD_OUT;
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else
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else
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next_state <= GET_WORD_IN;
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next_state <= GET_WORD_IN;
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MUX_WORD_OUT: if(almost_last_word & axis_downsizer_bus.tready)
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MUX_WORD_OUT: if(almost_last_word & axis_downsizer_bus.tready)
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next_state <= LAST_WORD_OUT;
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next_state <= LAST_WORD_OUT;
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else
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else
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next_state <= MUX_WORD_OUT;
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next_state <= MUX_WORD_OUT;
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LAST_WORD_OUT: if(~axis_downsizer_bus.tready)
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LAST_WORD_OUT: if(~axis_downsizer_bus.tready)
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next_state <= LAST_WORD_OUT;
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next_state <= LAST_WORD_OUT;
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else if(axis_in.tvalid)
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else if(axis_in.tvalid)
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next_state <= MUX_WORD_OUT;
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next_state <= MUX_WORD_OUT;
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else
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else
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next_state <= GET_WORD_IN;
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next_state <= GET_WORD_IN;
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default: next_state <= GET_WORD_IN;
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default: next_state <= GET_WORD_IN;
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endcase
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endcase
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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reg [(8*N)-1:0] tdata_r;
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reg [(8*N)-1:0] tdata_r;
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reg [I-1:0] tid_r;
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reg [I-1:0] tid_r;
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reg [D-1:0] tdest_r;
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reg [D-1:0] tdest_r;
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reg tlast_r;
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reg tlast_r;
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reg [U-1:0] tuser_r;
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reg [U-1:0] tuser_r;
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always_ff @(posedge aclk)
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always_ff @(posedge aclk)
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if(axis_in.tvalid & axis_in.tready)
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if(axis_in.tvalid & axis_in.tready)
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begin
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begin
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tdata_r <= axis_in.tdata;
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tdata_r <= axis_in.tdata;
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tid_r <= axis_in.tid;
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tid_r <= axis_in.tid;
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tdest_r <= axis_in.tdest;
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tdest_r <= axis_in.tdest;
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tlast_r <= axis_in.tlast; // packet width % S == 0 else tlast becomes invalid
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tlast_r <= axis_in.tlast; // packet width % S == 0 else tlast becomes invalid
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tuser_r <= axis_in.tuser;
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tuser_r <= axis_in.tuser;
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end
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end
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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reg [M_A-1:0] select;
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reg [M_A-1:0] select;
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assign almost_last_word = (select == S - 2);
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assign almost_last_word = (select == S - 2);
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always_ff @(posedge aclk)
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always_ff @(posedge aclk)
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if(~aresetn | (state == GET_WORD_IN))
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if(~aresetn | (state == GET_WORD_IN))
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select <= 0;
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select <= 0;
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else if(axis_downsizer_bus.tvalid & axis_downsizer_bus.tready)
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else if(axis_downsizer_bus.tvalid & axis_downsizer_bus.tready)
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select <= select + 1;
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select <= select + 1;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire [M_NW-1:0] mux_in_tdata [M_D-1:0];
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wire [M_NW-1:0] mux_in_tdata [M_D-1:0];
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wire [M_NW-1:0] mux_out_tdata;
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wire [M_NW-1:0] mux_out_tdata;
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recursive_mux #(.A(M_A), .W(M_NW))
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recursive_mux #(.A(M_A), .W(M_NW))
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tdata_mux_i(.data_in(mux_in_tdata), .data_out(mux_out_tdata), .*);
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tdata_mux_i(.data_in(mux_in_tdata), .data_out(mux_out_tdata), .*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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genvar j;
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generate
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generate
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for(j = 0; j < M_D; j++)
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begin: tdata_gen
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begin: tdata_gen
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for(genvar j = 0; j < M_D; j++)
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assign mux_in_tdata[j] = tdata_r[j*M_NW +: M_NW];
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assign mux_in_tdata[j] = tdata_r[j*M_NW +: M_NW];
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end
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end
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endgenerate
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endgenerate
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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generate
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generate
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begin: tuser_gen
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begin : tuser_gen
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if(BYTES_PER_TUSER != 0)
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if(BYTES_PER_TUSER != 0)
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begin
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begin : tuser_tuser_0_gen
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wire [M_UW-1:0] mux_in_tuser [M_D-1:0];
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wire [M_UW-1:0] mux_in_tuser [M_D-1:0];
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recursive_mux #(.A(M_A), .W(M_UW))
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recursive_mux #(.A(M_A), .W(M_UW))
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tuser_mux_i(.data_in(mux_in_tuser), .data_out(axis_downsizer_bus.tuser), .*);
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tuser_mux_i(.data_in(mux_in_tuser), .data_out(axis_downsizer_bus.tuser), .*);
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for(genvar j = 0; j < M_D; j++)
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for(j = 0; j < M_D; j++)
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begin : tuser_j_gen
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assign mux_in_tuser[j] = tuser_r[j*M_UW +: M_UW] & {M_UW{axis_downsizer_bus.tvalid}};
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assign mux_in_tuser[j] = tuser_r[j*M_UW +: M_UW] & {M_UW{axis_downsizer_bus.tvalid}};
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end
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end
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end
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else
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else
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begin : tuser_tuser_gen
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assign axis_downsizer_bus.tuser = tuser_r & {U{axis_downsizer_bus.tvalid}};
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assign axis_downsizer_bus.tuser = tuser_r & {U{axis_downsizer_bus.tvalid}};
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end
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end
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end
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endgenerate
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endgenerate
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign axis_in.tready = (state == GET_WORD_IN) |
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assign axis_in.tready = (state == GET_WORD_IN) |
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((state == LAST_WORD_OUT) & (next_state == MUX_WORD_OUT));
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((state == LAST_WORD_OUT) & (next_state == MUX_WORD_OUT));
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assign axis_downsizer_bus.tvalid = (state != GET_WORD_IN);
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assign axis_downsizer_bus.tvalid = (state != GET_WORD_IN);
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assign axis_downsizer_bus.tdata = mux_out_tdata;
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assign axis_downsizer_bus.tdata = mux_out_tdata;
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assign axis_downsizer_bus.tid = tid_r;
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assign axis_downsizer_bus.tid = tid_r;
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assign axis_downsizer_bus.tdest = tdest_r;
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assign axis_downsizer_bus.tdest = tdest_r;
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assign axis_downsizer_bus.tlast = (select == S - 1) ? tlast_r : 1'b0;
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assign axis_downsizer_bus.tlast = (select == S - 1) ? tlast_r : 1'b0;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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axis_register_slice #(.N(N), .U(U))
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axis_register_slice #(.N(N), .U(U))
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axis_register_slice_i(.axis_in(axis_downsizer_bus), .*);
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axis_register_slice_i(.axis_in(axis_downsizer_bus), .*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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