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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_if.sv] - Diff between revs 23 and 31

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Rev 23 Rev 31
Line 27... Line 27...
 
 
 
 
interface
interface
  axis_if
  axis_if
  #(
  #(
    N = 8,  // data bus width in bytes
    N = 0,  // data bus width in bytes
    I = 1,  // TID width
    I = 1,  // TID width
    D = 1,  // TDEST width
    D = 1,  // TDEST width
    U = 1   // TUSER width
    U = 1   // TUSER width
  )
  )
  (
  (
Line 48... Line 48...
    wire  [D-1:0]     tdest;
    wire  [D-1:0]     tdest;
    wire  [U-1:0]     tuser;
    wire  [U-1:0]     tuser;
 
 
 
 
    // --------------------------------------------------------------------
    // --------------------------------------------------------------------
    //
// synthesis translate_off
    default clocking cb_m @(posedge aclk iff aresetn);
    default clocking cb_m @(posedge aclk iff aresetn);
      input   aresetn;
 
      input   aclk;
 
      output  tvalid;
      output  tvalid;
      input   tready;
      input   tready;
      output  tdata;
      output  tdata;
      output  tstrb;
      output  tstrb;
      output  tkeep;
      output  tkeep;
Line 67... Line 65...
 
 
 
 
    // --------------------------------------------------------------------
    // --------------------------------------------------------------------
    //
    //
    clocking cb_s @(posedge aclk iff aresetn);
    clocking cb_s @(posedge aclk iff aresetn);
      input   aresetn;
 
      input   aclk;
 
      input   tvalid;
      input   tvalid;
      output  tready;
      output  tready;
      input   tdata;
      input   tdata;
      input   tstrb;
      input   tstrb;
      input   tkeep;
      input   tkeep;
      input   tlast;
      input   tlast;
      input   tid;
      input   tid;
      input   tdest;
      input   tdest;
      input   tuser;
      input   tuser;
    endclocking
    endclocking
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
 
 
 
    // --------------------------------------------------------------------
    // --------------------------------------------------------------------
    //
    //
 
`ifdef USE_MOD_PORTS
    modport
    modport
      master
      master
      (
      (
 
// --------------------------------------------------------------------
 
// synthesis translate_off
 
          clocking  cb_m,
 
// synthesis translate_on
 
// --------------------------------------------------------------------
        input     aresetn,
        input     aresetn,
        input     aclk,
        input     aclk,
        output    tvalid,
        output    tvalid,
        input     tready,
        input     tready,
        output    tdata,
        output    tdata,
        output    tstrb,
        output    tstrb,
        output    tkeep,
        output    tkeep,
        output    tlast,
        output    tlast,
        output    tid,
        output    tid,
        output    tdest,
        output    tdest,
        output    tuser,
        output    tuser
        clocking  cb_m
 
      );
      );
 
 
 
 
    // --------------------------------------------------------------------
    // --------------------------------------------------------------------
    //
    //
    modport
    modport
      slave
      slave
      (
      (
 
// --------------------------------------------------------------------
 
// synthesis translate_off
 
          clocking  cb_s,
 
// synthesis translate_on
 
// --------------------------------------------------------------------
        input     aresetn,
        input     aresetn,
        input     aclk,
        input     aclk,
        input     tvalid,
        input     tvalid,
        output    tready,
        output    tready,
        input     tdata,
        input     tdata,
        input     tstrb,
        input     tstrb,
        input     tkeep,
        input     tkeep,
        input     tlast,
        input     tlast,
        input     tid,
        input     tid,
        input     tdest,
        input     tdest,
        input     tuser,
        input     tuser
        clocking  cb_s
 
      );
      );
 
`endif
 
 
 
 
endinterface: axis_if
// --------------------------------------------------------------------
 
// synthesis translate_off
 
  task
 
    zero_cycle_delay;
 
 
 
    ##0;
 
 
 
  endtask: zero_cycle_delay
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
 
 
 
 
// --------------------------------------------------------------------
 
//
 
endinterface: axis_if
 
 

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