| Line 27... |
Line 27... |
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interface
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interface
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axis_if
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axis_if
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#(
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#(
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N = 8, // data bus width in bytes
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N = 0, // data bus width in bytes
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I = 1, // TID width
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I = 1, // TID width
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D = 1, // TDEST width
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D = 1, // TDEST width
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U = 1 // TUSER width
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U = 1 // TUSER width
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)
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)
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(
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(
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| Line 48... |
Line 48... |
wire [D-1:0] tdest;
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wire [D-1:0] tdest;
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wire [U-1:0] tuser;
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wire [U-1:0] tuser;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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// synthesis translate_off
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default clocking cb_m @(posedge aclk iff aresetn);
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default clocking cb_m @(posedge aclk iff aresetn);
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input aresetn;
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input aclk;
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output tvalid;
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output tvalid;
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input tready;
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input tready;
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output tdata;
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output tdata;
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output tstrb;
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output tstrb;
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output tkeep;
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output tkeep;
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| Line 67... |
Line 65... |
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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clocking cb_s @(posedge aclk iff aresetn);
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clocking cb_s @(posedge aclk iff aresetn);
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input aresetn;
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input aclk;
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input tvalid;
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input tvalid;
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output tready;
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output tready;
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input tdata;
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input tdata;
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input tstrb;
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input tstrb;
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input tkeep;
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input tkeep;
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input tlast;
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input tlast;
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input tid;
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input tid;
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input tdest;
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input tdest;
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input tuser;
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input tuser;
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endclocking
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endclocking
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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`ifdef USE_MOD_PORTS
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modport
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modport
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master
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master
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(
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(
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// --------------------------------------------------------------------
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// synthesis translate_off
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clocking cb_m,
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// synthesis translate_on
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// --------------------------------------------------------------------
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input aresetn,
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input aresetn,
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input aclk,
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input aclk,
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output tvalid,
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output tvalid,
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input tready,
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input tready,
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output tdata,
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output tdata,
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output tstrb,
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output tstrb,
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output tkeep,
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output tkeep,
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output tlast,
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output tlast,
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output tid,
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output tid,
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output tdest,
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output tdest,
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output tuser,
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output tuser
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clocking cb_m
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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modport
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modport
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slave
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slave
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(
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(
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// --------------------------------------------------------------------
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// synthesis translate_off
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clocking cb_s,
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// synthesis translate_on
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// --------------------------------------------------------------------
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input aresetn,
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input aresetn,
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input aclk,
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input aclk,
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input tvalid,
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input tvalid,
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output tready,
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output tready,
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input tdata,
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input tdata,
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input tstrb,
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input tstrb,
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input tkeep,
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input tkeep,
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input tlast,
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input tlast,
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input tid,
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input tid,
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input tdest,
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input tdest,
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input tuser,
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input tuser
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clocking cb_s
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);
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);
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`endif
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endinterface: axis_if
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// --------------------------------------------------------------------
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// synthesis translate_off
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task
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zero_cycle_delay;
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##0;
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endtask: zero_cycle_delay
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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endinterface: axis_if
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