//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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interface
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interface
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axis_if
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axis_if
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#(
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#(
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N = 8, // data bus width in bytes
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N = 0, // data bus width in bytes
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I = 1, // TID width
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I = 1, // TID width
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D = 1, // TDEST width
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D = 1, // TDEST width
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U = 1 // TUSER width
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U = 1 // TUSER width
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)
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)
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(
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(
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input aclk,
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input aclk,
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input aresetn
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input aresetn
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);
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);
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wire tvalid;
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wire tvalid;
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wire tready;
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wire tready;
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wire [(8*N)-1:0] tdata;
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wire [(8*N)-1:0] tdata;
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wire [N-1:0] tstrb;
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wire [N-1:0] tstrb;
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wire [N-1:0] tkeep;
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wire [N-1:0] tkeep;
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wire tlast;
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wire tlast;
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wire [I-1:0] tid;
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wire [I-1:0] tid;
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wire [D-1:0] tdest;
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wire [D-1:0] tdest;
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wire [U-1:0] tuser;
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wire [U-1:0] tuser;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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// synthesis translate_off
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default clocking cb_m @(posedge aclk iff aresetn);
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default clocking cb_m @(posedge aclk iff aresetn);
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input aresetn;
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input aclk;
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output tvalid;
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output tvalid;
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input tready;
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input tready;
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output tdata;
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output tdata;
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output tstrb;
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output tstrb;
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output tkeep;
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output tkeep;
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output tlast;
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output tlast;
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output tid;
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output tid;
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output tdest;
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output tdest;
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output tuser;
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output tuser;
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endclocking
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endclocking
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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clocking cb_s @(posedge aclk iff aresetn);
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clocking cb_s @(posedge aclk iff aresetn);
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input aresetn;
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input aclk;
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input tvalid;
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input tvalid;
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output tready;
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output tready;
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input tdata;
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input tdata;
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input tstrb;
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input tstrb;
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input tkeep;
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input tkeep;
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input tlast;
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input tlast;
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input tid;
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input tid;
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input tdest;
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input tdest;
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input tuser;
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input tuser;
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endclocking
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endclocking
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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`ifdef USE_MOD_PORTS
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modport
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modport
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master
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master
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(
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(
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// --------------------------------------------------------------------
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// synthesis translate_off
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clocking cb_m,
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// synthesis translate_on
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// --------------------------------------------------------------------
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input aresetn,
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input aresetn,
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input aclk,
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input aclk,
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output tvalid,
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output tvalid,
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input tready,
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input tready,
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output tdata,
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output tdata,
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output tstrb,
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output tstrb,
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output tkeep,
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output tkeep,
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output tlast,
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output tlast,
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output tid,
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output tid,
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output tdest,
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output tdest,
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output tuser,
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output tuser
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clocking cb_m
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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modport
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modport
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slave
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slave
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(
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(
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// --------------------------------------------------------------------
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// synthesis translate_off
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clocking cb_s,
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// synthesis translate_on
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// --------------------------------------------------------------------
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input aresetn,
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input aresetn,
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input aclk,
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input aclk,
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input tvalid,
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input tvalid,
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output tready,
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output tready,
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input tdata,
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input tdata,
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input tstrb,
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input tstrb,
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input tkeep,
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input tkeep,
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input tlast,
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input tlast,
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input tid,
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input tid,
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input tdest,
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input tdest,
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input tuser,
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input tuser
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clocking cb_s
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);
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);
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`endif
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endinterface: axis_if
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// --------------------------------------------------------------------
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// synthesis translate_off
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task
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zero_cycle_delay;
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##0;
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endtask: zero_cycle_delay
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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endinterface: axis_if
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