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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_if.sv] - Diff between revs 31 and 35

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
interface
interface
  axis_if
  axis_if
  #(
  #(
    N = 0,  // data bus width in bytes
    N,  // data bus width in bytes
    I = 1,  // TID width
    I = 1,  // TID width
    D = 1,  // TDEST width
    D = 1,  // TDEST width
    U = 1   // TUSER width
    U = 1   // TUSER width
  )
  )
  (
  (
    input             aclk,
    input             aclk,
    input             aresetn
    input             aresetn
  );
  );
  wire              tvalid;
  wire              tvalid;
  wire              tready;
  wire              tready;
  wire  [(8*N)-1:0] tdata;
  wire  [(8*N)-1:0] tdata;
  wire  [N-1:0]     tstrb;
  wire  [N-1:0]     tstrb;
  wire  [N-1:0]     tkeep;
  wire  [N-1:0]     tkeep;
  wire              tlast;
  wire              tlast;
  wire  [I-1:0]     tid;
  wire  [I-1:0]     tid;
  wire  [D-1:0]     tdest;
  wire  [D-1:0]     tdest;
  wire  [U-1:0]     tuser;
  wire  [U-1:0]     tuser;
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
// synthesis translate_off
  default clocking cb_m @(posedge aclk iff aresetn);
  default clocking cb_m @(posedge aclk iff aresetn);
    output  tvalid;
    output  tvalid;
    input   tready;
    input   tready;
    output  tdata;
    output  tdata;
    output  tstrb;
    output  tstrb;
    output  tkeep;
    output  tkeep;
    output  tlast;
    output  tlast;
    output  tid;
    output  tid;
    output  tdest;
    output  tdest;
    output  tuser;
    output  tuser;
  endclocking
  endclocking
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  clocking cb_s @(posedge aclk iff aresetn);
  clocking cb_s @(posedge aclk iff aresetn);
    input   tvalid;
    input   tvalid;
    output  tready;
    output  tready;
    input   tdata;
    input   tdata;
    input   tstrb;
    input   tstrb;
    input   tkeep;
    input   tkeep;
    input   tlast;
    input   tlast;
    input   tid;
    input   tid;
    input   tdest;
    input   tdest;
    input   tuser;
    input   tuser;
  endclocking
  endclocking
// synthesis translate_on
// synthesis translate_on
// --------------------------------------------------------------------
// --------------------------------------------------------------------
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
`ifdef USE_MOD_PORTS
`ifdef USE_MOD_PORTS
    modport
    modport
      master
      master
      (
      (
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
// synthesis translate_off
          clocking  cb_m,
          clocking  cb_m,
// synthesis translate_on
// synthesis translate_on
// --------------------------------------------------------------------
// --------------------------------------------------------------------
        input     aresetn,
        input     aresetn,
        input     aclk,
        input     aclk,
        output    tvalid,
        output    tvalid,
        input     tready,
        input     tready,
        output    tdata,
        output    tdata,
        output    tstrb,
        output    tstrb,
        output    tkeep,
        output    tkeep,
        output    tlast,
        output    tlast,
        output    tid,
        output    tid,
        output    tdest,
        output    tdest,
        output    tuser
        output    tuser
      );
      );
    // --------------------------------------------------------------------
    // --------------------------------------------------------------------
    //
    //
    modport
    modport
      slave
      slave
      (
      (
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
// synthesis translate_off
          clocking  cb_s,
          clocking  cb_s,
// synthesis translate_on
// synthesis translate_on
// --------------------------------------------------------------------
// --------------------------------------------------------------------
        input     aresetn,
        input     aresetn,
        input     aclk,
        input     aclk,
        input     tvalid,
        input     tvalid,
        output    tready,
        output    tready,
        input     tdata,
        input     tdata,
        input     tstrb,
        input     tstrb,
        input     tkeep,
        input     tkeep,
        input     tlast,
        input     tlast,
        input     tid,
        input     tid,
        input     tdest,
        input     tdest,
        input     tuser
        input     tuser
      );
      );
`endif
`endif
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
// synthesis translate_off
  task
  task
    zero_cycle_delay;
    zero_cycle_delay;
    ##0;
    ##0;
  endtask: zero_cycle_delay
  endtask: zero_cycle_delay
// synthesis translate_on
// synthesis translate_on
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
//
endinterface: axis_if
endinterface: axis_if
 
 

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