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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_map_fifo.sv] - Diff between revs 36 and 37

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Rev 36 Rev 37
Line 27... Line 27...
 
 
module
module
  axis_map_fifo
  axis_map_fifo
  #(
  #(
    N,              // data bus width in bytes
    N,              // data bus width in bytes
    I = 0,          // TID width
    I = 1,          // TID width
    D = 0,          // TDEST width
    D = 1,          // TDEST width
    U = 1,          // TUSER width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0,  //  set to 1 to enable, 0 to disable
    USE_XID = 0,    //  set to 1 to enable, 0 to disable
    // USE_XID = 0,    //  set to 1 to enable, 0 to disable
    W = 0
    W = 0
  )
  )
  (
  (
    axis_if         axis_in,
    axis_if         axis_in,
    axis_if         axis_out,
    axis_if         axis_out,
Line 48... Line 48...
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
// synthesis translate_off
  initial
  initial
  begin
  begin
    a_tid_unsuported:   assert(I == 0) else $fatal;
    // a_tid_unsuported:   assert(I == 0) else $fatal;
    a_tdest_unsuported: assert(D == 0) else $fatal;
    // a_tdest_unsuported: assert(D == 0) else $fatal;
    a_xid_unsuported: assert(USE_XID == 0) else $fatal;
    // a_xid_unsuported: assert(USE_XID == 0) else $fatal;
    a_w: assert(W == (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1) else $fatal;
    a_w: assert(W == (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1) else $fatal;
  end
  end
// synthesis translate_on
// synthesis translate_on
// --------------------------------------------------------------------
// --------------------------------------------------------------------
 
 
Line 65... Line 65...
    begin: assign_gen
    begin: assign_gen
      if(USE_TSTRB & USE_TKEEP)
      if(USE_TSTRB & USE_TKEEP)
      begin
      begin
        assign wr_data =
        assign wr_data =
          {
          {
            axis_in.tdata,
 
            axis_in.tlast,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tuser,
            axis_in.tstrb,
            axis_in.tstrb,
            axis_in.tkeep
            axis_in.tkeep,
 
            axis_in.tdata
          };
          };
        assign
        assign
          {
          {
            axis_out.tdata,
 
            axis_out.tlast,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tuser,
            axis_out.tstrb,
            axis_out.tstrb,
            axis_out.tkeep
            axis_out.tkeep,
 
            axis_out.tdata
          } = rd_data;
          } = rd_data;
      end
      end
      else if(USE_TSTRB)
      else if(USE_TSTRB)
      begin
      begin
        assign wr_data =
        assign wr_data =
          {
          {
            axis_in.tdata,
 
            axis_in.tlast,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tuser,
            axis_in.tstrb
            axis_in.tstrb,
 
            axis_in.tdata
          };
          };
        assign
        assign
          {
          {
            axis_out.tdata,
 
            axis_out.tlast,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tuser,
            axis_out.tstrb
            axis_out.tstrb,
 
            axis_out.tdata
          } = rd_data;
          } = rd_data;
      end
      end
      else if(USE_TKEEP)
      else if(USE_TKEEP)
      begin
      begin
        assign wr_data =
        assign wr_data =
          {
          {
            axis_in.tdata,
 
            axis_in.tlast,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tuser,
            axis_in.tkeep
            axis_in.tkeep,
 
            axis_in.tdata
          };
          };
        assign
        assign
          {
          {
            axis_out.tdata,
 
            axis_out.tlast,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tuser,
            axis_out.tkeep
            axis_out.tkeep,
 
            axis_out.tdata
          } = rd_data;
          } = rd_data;
      end
      end
      else
      else
      begin
      begin
        assign wr_data =
        assign wr_data =
          {
          {
            axis_in.tdata,
 
            axis_in.tlast,
            axis_in.tlast,
            axis_in.tuser
            axis_in.tuser,
 
            axis_in.tdata
          };
          };
        assign
        assign
          {
          {
            axis_out.tdata,
 
            axis_out.tlast,
            axis_out.tlast,
            axis_out.tuser
            axis_out.tuser,
 
            axis_out.tdata
          } = rd_data;
          } = rd_data;
      end
      end
    end
    end
  endgenerate
  endgenerate
 
 

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