Line 27... |
Line 27... |
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module
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module
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axis_map_fifo
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axis_map_fifo
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#(
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#(
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N, // data bus width in bytes
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N, // data bus width in bytes
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I = 0, // TID width
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I = 1, // TID width
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D = 0, // TDEST width
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D = 1, // TDEST width
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U = 1, // TUSER width
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U = 1, // TUSER width
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TKEEP = 0, // set to 1 to enable, 0 to disable
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USE_TKEEP = 0, // set to 1 to enable, 0 to disable
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USE_XID = 0, // set to 1 to enable, 0 to disable
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// USE_XID = 0, // set to 1 to enable, 0 to disable
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W = 0
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W = 0
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)
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)
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(
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(
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axis_if axis_in,
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axis_if axis_in,
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axis_if axis_out,
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axis_if axis_out,
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Line 48... |
Line 48... |
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// synthesis translate_off
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// synthesis translate_off
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initial
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initial
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begin
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begin
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a_tid_unsuported: assert(I == 0) else $fatal;
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// a_tid_unsuported: assert(I == 0) else $fatal;
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a_tdest_unsuported: assert(D == 0) else $fatal;
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// a_tdest_unsuported: assert(D == 0) else $fatal;
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a_xid_unsuported: assert(USE_XID == 0) else $fatal;
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// a_xid_unsuported: assert(USE_XID == 0) else $fatal;
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a_w: assert(W == (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1) else $fatal;
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a_w: assert(W == (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1) else $fatal;
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end
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end
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// synthesis translate_on
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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Line 65... |
Line 65... |
begin: assign_gen
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begin: assign_gen
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if(USE_TSTRB & USE_TKEEP)
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if(USE_TSTRB & USE_TKEEP)
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begin
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begin
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assign wr_data =
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assign wr_data =
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{
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{
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axis_in.tdata,
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axis_in.tlast,
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axis_in.tlast,
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axis_in.tuser,
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axis_in.tuser,
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axis_in.tstrb,
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axis_in.tstrb,
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axis_in.tkeep
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axis_in.tkeep,
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axis_in.tdata
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};
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};
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assign
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assign
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{
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{
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axis_out.tdata,
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axis_out.tlast,
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axis_out.tlast,
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axis_out.tuser,
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axis_out.tuser,
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axis_out.tstrb,
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axis_out.tstrb,
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axis_out.tkeep
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axis_out.tkeep,
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axis_out.tdata
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} = rd_data;
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} = rd_data;
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end
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end
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else if(USE_TSTRB)
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else if(USE_TSTRB)
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begin
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begin
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assign wr_data =
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assign wr_data =
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{
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{
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axis_in.tdata,
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axis_in.tlast,
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axis_in.tlast,
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axis_in.tuser,
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axis_in.tuser,
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axis_in.tstrb
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axis_in.tstrb,
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axis_in.tdata
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};
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};
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assign
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assign
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{
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{
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axis_out.tdata,
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axis_out.tlast,
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axis_out.tlast,
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axis_out.tuser,
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axis_out.tuser,
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axis_out.tstrb
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axis_out.tstrb,
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axis_out.tdata
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} = rd_data;
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} = rd_data;
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end
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end
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else if(USE_TKEEP)
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else if(USE_TKEEP)
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begin
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begin
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assign wr_data =
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assign wr_data =
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{
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{
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axis_in.tdata,
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axis_in.tlast,
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axis_in.tlast,
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axis_in.tuser,
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axis_in.tuser,
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axis_in.tkeep
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axis_in.tkeep,
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axis_in.tdata
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};
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};
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assign
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assign
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{
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{
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axis_out.tdata,
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axis_out.tlast,
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axis_out.tlast,
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axis_out.tuser,
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axis_out.tuser,
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axis_out.tkeep
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axis_out.tkeep,
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axis_out.tdata
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} = rd_data;
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} = rd_data;
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end
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end
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else
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else
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begin
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begin
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assign wr_data =
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assign wr_data =
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{
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{
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axis_in.tdata,
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axis_in.tlast,
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axis_in.tlast,
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axis_in.tuser
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axis_in.tuser,
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axis_in.tdata
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};
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};
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assign
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assign
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{
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{
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axis_out.tdata,
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axis_out.tlast,
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axis_out.tlast,
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axis_out.tuser
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axis_out.tuser,
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axis_out.tdata
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} = rd_data;
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} = rd_data;
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end
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end
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end
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end
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endgenerate
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endgenerate
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