//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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axis_switch_allocator
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axis_switch_allocator
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#(
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#(
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N, // data bus width in bytes
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N, // data bus width in bytes
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I = 1, // TID width
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I = 1, // TID width
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D = 1, // TDEST width
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D = 1, // TDEST width
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U = 1, // TUSER width
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U = 1, // TUSER width
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U_IS_EOP = -1, // set to -1 for tlast, else set to index of tuser
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U_IS_EOP = -1, // set to -1 for tlast, else set to index of tuser
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SA, // select width
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SA, // select width
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SD = 2 ** SA
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SD = 2 ** SA
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)
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)
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(
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(
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axis_if axis_in,
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axis_if axis_in,
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axis_if axis_out[SD-1:0],
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axis_if axis_out[SD-1:0],
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input aclk,
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input aclk,
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input aresetn
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input aresetn
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire eop_in;
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axis_eop_set #(U_IS_EOP)
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axis_eop_set_i
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(
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.axis_in(axis_in),
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.tready(axis_switch_in.tready),
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.tvalid(axis_in.tvalid),
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.axis_eop(eop_in),
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.*
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);
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// --------------------------------------------------------------------
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//
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wire eop_out_mux;
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wire eop_out_mux;
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reg [SA-1:0] select;
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reg [SA-1:0] select;
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axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(SA))
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axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(SA))
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axis_eop_mux_i
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axis_eop_mux_i
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(
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(
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.axis_in(axis_out),
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.axis_in(axis_out),
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.axis_eop(eop_out_mux),
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.axis_eop(eop_out_mux),
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.*
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.*
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_switch_in(.*);
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axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_switch_in(.*);
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axis_alias #(.CONNECT_TREADY(0), .CONNECT_TVALID(0))
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axis_alias #(.CONNECT_TREADY(0), .CONNECT_TVALID(0))
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axis_alias_i(.axis_out(axis_switch_in), .*);
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axis_alias_i(.axis_out(axis_switch_in), .*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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wire eop_in;
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axis_eop_set #(U_IS_EOP)
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axis_eop_set_i
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(
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.axis_in(axis_in),
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.tready(axis_switch_in.tready),
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.tvalid(axis_in.tvalid),
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.axis_eop(eop_in),
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.*
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);
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// --------------------------------------------------------------------
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// state machine binary definitions
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// state machine binary definitions
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enum reg [3:0]
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enum reg [3:0]
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{
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{
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ALLOT = 4'b0001,
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ALLOT = 4'b0001,
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FLUSH = 4'b0010,
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FLUSH = 4'b0010,
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SWITCH = 4'b0100,
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SWITCH = 4'b0100,
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SETTLE = 4'b1000
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SETTLE = 4'b1000
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} state, next_state;
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} state, next_state;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// state machine flop
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// state machine flop
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always_ff @(posedge aclk)
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always_ff @(posedge aclk)
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if(~aresetn)
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if(~aresetn)
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state <= ALLOT;
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state <= ALLOT;
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else
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else
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state <= next_state;
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state <= next_state;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// state machine
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// state machine
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always_comb
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always_comb
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case(state)
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case(state)
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ALLOT: if(eop_in)
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ALLOT: if(eop_in)
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next_state <= FLUSH;
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next_state <= FLUSH;
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else
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else
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next_state <= ALLOT;
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next_state <= ALLOT;
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FLUSH: if(eop_out_mux)
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FLUSH: if(eop_out_mux)
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next_state <= SWITCH;
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next_state <= SWITCH;
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else
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else
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next_state <= FLUSH;
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next_state <= FLUSH;
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SWITCH: next_state <= SETTLE;
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SWITCH: next_state <= SETTLE;
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SETTLE: next_state <= ALLOT; // let select propagate to the switches
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SETTLE: next_state <= ALLOT; // let select propagate to the switches
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default: next_state <= ALLOT;
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default: next_state <= ALLOT;
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endcase
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endcase
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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always_ff @(posedge aclk)
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always_ff @(posedge aclk)
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if(~aresetn)
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if(~aresetn)
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select <= 0;
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select <= 0;
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else if(state == SWITCH)
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else if(state == SWITCH)
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select <= select + 1;
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select <= select + 1;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA))
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recursive_axis_switch #(.N(N), .I(I), .D(D), .U(U), .SA(SA))
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recursive_axis_switch_i(.axis_in(axis_switch_in), .*);
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recursive_axis_switch_i(.axis_in(axis_switch_in), .*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign axis_in.tready = (state == ALLOT) & axis_switch_in.tready;
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assign axis_in.tready = (state == ALLOT) & axis_switch_in.tready;
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assign axis_switch_in.tvalid = (state == ALLOT) & axis_in.tvalid;
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assign axis_switch_in.tvalid = (state == ALLOT) & axis_in.tvalid;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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