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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module
module
  sync_fifo
  sync_fifo
  #(
  #(
    W = 8,
    W = 8,
    D = 16,
    D = 16,
    UB = $clog2(D)
    UB = $clog2(D)
  )
  )
  (
  (
    output            wr_full,
    output            wr_full,
    input   [W-1:0]   wr_data,
    input   [W-1:0]   wr_data,
    input             wr_en,
    input             wr_en,
    output            rd_empty,
    output            rd_empty,
    output  [W-1:0]   rd_data,
    output  [W-1:0]   rd_data,
    input             rd_en,
    input             rd_en,
    output  [UB:0]    count,
    output  [UB:0]    count,
    input             clk,
    input             clk,
    input             reset
    input             reset
  );
  );
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  generate
  generate
    begin: fifo_gen
    begin: fifo_gen
      if(D == 2)
      if(D == 2)
      begin
      begin
        assign count = 0;
        assign count = 0;
        tiny_sync_fifo #(.W(W))
        tiny_sync_fifo #(.W(W))
          tiny_sync_fifo_i(.*);
          tiny_sync_fifo_i(.*);
      end
      end
      else
      else
      begin
      begin
        bc_sync_fifo #(.depth(D), .width(W))
        bc_sync_fifo #(.depth(D), .width(W))
          bc_sync_fifo_i
          bc_sync_fifo_i
          (
          (
            .wr_enable(wr_en),
            .wr_enable(wr_en),
            .rd_enable(rd_en),
            .rd_enable(rd_en),
            .empty(rd_empty),
            .empty(rd_empty),
            .full(wr_full),
            .full(wr_full),
            .count(count),
            .count(count),
            .*
            .*
           );
           );
      end
      end
    end
    end
  endgenerate
  endgenerate
// --------------------------------------------------------------------
// --------------------------------------------------------------------
 
// synthesis translate_off
 
  always_ff @(posedge clk)
 
    if(wr_en & wr_full)
 
      $stop;
 
  always_ff @(posedge clk)
 
    if(rd_en & rd_empty)
 
      $stop;
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
 
 
 
 
// --------------------------------------------------------------------
//
//
endmodule
endmodule
 
 

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