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Line 1... Line 1...
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    eqspiflashsim.cpp
// Filename:    eqspiflashsim.cpp
//
//
// Project:     OpenArty, an entirely open SoC based upon the Arty platform
// Project:     Wishbone Controlled Quad SPI Flash Controller
//
//
// Purpose:     This library simulates the operation of a Quad-SPI commanded
// Purpose:     This library simulates the operation of a Quad-SPI commanded
//              flash, such as the Micron N25Q128A used on the Arty development
//              flash, such as the Micron N25Q128A used on the Arty development
//              board by Digilent.  As such, it is defined by 16 MBytes of
//              board by Digilent.  As such, it is defined by 16 MBytes of
//              memory (4 MWord).
//              memory (4 MWord).
Line 16... Line 16...
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
Line 29... Line 29...
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
// You should have received a copy of the GNU General Public License along
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
// <http://www.gnu.org/licenses/> for a copy.
//
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
Line 44... Line 44...
//
//
#include <stdio.h>
#include <stdio.h>
#include <string.h>
#include <string.h>
#include <assert.h>
#include <assert.h>
#include <stdlib.h>
#include <stdlib.h>
 
#include <stdint.h>
 
 
#include "eqspiflashsim.h"
#include "eqspiflashsim.h"
 
 
#define MEMBYTES        (1<<24)
 
 
 
static  const unsigned
static  const unsigned
        DEVESD = 0x014,
        DEVESD = 0x014,
        // MICROSECONDS = 200,
        // MICROSECONDS = 200,
        // MILLISECONDS = MICROSECONDS * 1000,
        // MILLISECONDS = MICROSECONDS * 1000,
        // SECONDS = MILLISECONDS * 1000,
        // SECONDS = MILLISECONDS * 1000,
Line 89... Line 88...
                (char)0xf8, (char)0xf7, (char)0xf6, (char)0xf5,
                (char)0xf8, (char)0xf7, (char)0xf6, (char)0xf5,
                (char)0xf4, (char)0xf3, (char)0xf2, (char)0xf1,
                (char)0xf4, (char)0xf3, (char)0xf2, (char)0xf1,
                (char)0xf0, (char)0xef
                (char)0xf0, (char)0xef
        };
        };
 
 
EQSPIFLASHSIM::EQSPIFLASHSIM(void) {
EQSPIFLASHSIM::EQSPIFLASHSIM(const int lglen, bool debug) {
        const   int     NSECTORS = MEMBYTES>>16;
        int     nsectors;
        m_mem = new char[MEMBYTES];
        m_membytes = (1<<lglen);
 
        m_memmask = (m_membytes - 1);
 
        m_mem = new char[m_membytes];
        m_pmem = new char[256];
        m_pmem = new char[256];
        m_otp  = new char[65];
        m_otp  = new char[65];
        for(int i=0; i<65; i++)
        for(int i=0; i<65; i++)
                m_otp[i] = 0x0ff;
                m_otp[i] = 0x0ff;
        m_otp[64] = 1;
        m_otp[64] = 1;
        m_otp_wp = false;
        m_otp_wp = false;
        m_lockregs = new char[NSECTORS];
        nsectors = m_membytes>>16;
        for(int i=0; i<NSECTORS; i++)
        m_lockregs = new char[nsectors];
 
        for(int i=0; i<nsectors; i++)
                m_lockregs[i] = 0;
                m_lockregs[i] = 0;
 
 
        m_state = EQSPIF_IDLE;
        m_state = EQSPIF_IDLE;
        m_last_sck = 1;
        m_last_sck = 1;
        m_write_count = 0;
        m_write_count = 0;
        m_ireg = m_oreg = 0;
        m_ireg = m_oreg = 0;
        m_sreg = 0x01c;
        m_sreg = 0x01c;
        m_creg = 0x001; // Initial creg on delivery
        m_creg = 0x001; // Initial creg on delivery
        m_vconfig   = 0x7; // Volatile configuration register
        m_vconfig   = 0x83; // Volatile configuration register
        m_nvconfig = 0x0fff; // Nonvolatile configuration register
        m_nvconfig = 0x0fff; // Nonvolatile configuration register
        m_quad_mode = false;
        m_quad_mode = EQSPIF_QMODE_SPI;
        m_mode_byte = 0;
        m_mode_byte = 0;
        m_flagreg = 0x0a5;
        m_flagreg = 0x0a5;
 
 
        m_debug = true;
        m_debug = true;
 
 
        memset(m_mem, 0x0ff, MEMBYTES);
        memset(m_mem, 0x0ff, m_membytes);
}
}
 
 
void    EQSPIFLASHSIM::load(const unsigned addr, const char *fname) {
void    EQSPIFLASHSIM::load(const unsigned addr, const char *fname) {
        FILE    *fp;
        FILE    *fp;
        size_t  len;
        size_t  len, nr = 0;
 
 
        if (addr >= MEMBYTES)
        if (addr >= m_membytes)
                return; // return void
                return; // return void
        len = MEMBYTES-addr*4;
 
 
        // If not given, then length is from the given address until the end
 
        // of the flash memory
 
        len = m_membytes-addr*4;
 
 
        if (NULL != (fp = fopen(fname, "r"))) {
        if (NULL != (fp = fopen(fname, "r"))) {
                int     nr = 0;
 
                nr = fread(&m_mem[addr*4], sizeof(char), len, fp);
                nr = fread(&m_mem[addr*4], sizeof(char), len, fp);
                fclose(fp);
                fclose(fp);
                if (nr == 0) {
                if (nr == 0) {
                        fprintf(stderr, "SPI-FLASH: Could not read %s\n", fname);
                        fprintf(stderr, "EQSPI-FLASH: Could not read %s\n", fname);
                        perror("O/S Err:");
                        perror("O/S Err:");
                }
                }
        } else {
        } else {
                fprintf(stderr, "SPI-FLASH: Could not open %s\n", fname);
                fprintf(stderr, "EQSPI-FLASH: Could not open %s\n", fname);
                perror("O/S Err:");
                perror("O/S Err:");
        }
        }
 
 
 
        for(unsigned i=nr; i<m_membytes; i++)
 
                m_mem[i] = 0x0ff;
 
}
 
 
 
void    EQSPIFLASHSIM::load(const uint32_t offset, const char *data, const uint32_t len) {
 
        uint32_t        moff = (offset & (m_memmask));
 
 
 
        memcpy(&m_mem[moff], data, len);
}
}
 
 
#define QOREG(A)        m_oreg = ((m_oreg & (~0x0ff))|(A&0x0ff))
#define QOREG(A)        m_oreg = ((m_oreg & (~0x0ff))|(A&0x0ff))
 
 
int     EQSPIFLASHSIM::operator()(const int csn, const int sck, const int dat) {
int     EQSPIFLASHSIM::operator()(const int csn, const int sck, const int dat) {
Line 180... Line 193...
                                        m_mem[(m_addr&(~0x0ff))+i]&0x0ff, m_pmem[i]&0x0ff,
                                        m_mem[(m_addr&(~0x0ff))+i]&0x0ff, m_pmem[i]&0x0ff,
                                        m_mem[(m_addr&(~0x0ff))+i]& m_pmem[i]&0x0ff);
                                        m_mem[(m_addr&(~0x0ff))+i]& m_pmem[i]&0x0ff);
                                */
                                */
                                m_mem[(m_addr&(~0x0ff))+i] &= m_pmem[i];
                                m_mem[(m_addr&(~0x0ff))+i] &= m_pmem[i];
                        }
                        }
                        m_quad_mode = false;
                        m_quad_mode = EQSPIF_QMODE_SPI;
                } else if (EQSPIF_WRCR == m_state) {
                } else if (EQSPIF_WRCR == m_state) {
                        if (m_debug) printf("Actually writing volatile config register\n");
                        if (m_debug) printf("Actually writing volatile config register: VCONFIG = 0x%04x\n", m_vconfig);
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
                        m_state = EQSPIF_IDLE;
                        m_state = EQSPIF_IDLE;
                } else if (EQSPIF_WRNVCONFIG == m_state) {
                } else if (EQSPIF_WRNVCONFIG == m_state) {
                        if (m_debug) printf("Actually writing nonvolatile config register\n");
                        if (m_debug) printf("Actually writing nonvolatile config register: VCONFIG = 0x%02x\n", m_nvconfig);
                        m_write_count = tWNVCR;
                        m_write_count = tWNVCR;
                        m_state = EQSPIF_IDLE;
                        m_state = EQSPIF_IDLE;
                } else if (EQSPIF_WREVCONFIG == m_state) {
                } else if (EQSPIF_WREVCONFIG == m_state) {
                        if (m_debug) printf("Actually writing Enhanced volatile config register\n");
                        if (m_debug) printf("Actually writing Enhanced volatile config register\n");
                        m_state = EQSPIF_IDLE;
                        m_state = EQSPIF_IDLE;
Line 238... Line 251...
                        m_write_count = tBE;
                        m_write_count = tBE;
                        m_state = EQSPIF_IDLE;
                        m_state = EQSPIF_IDLE;
                        m_sreg &= (~EQSPIF_WEL_FLAG);
                        m_sreg &= (~EQSPIF_WEL_FLAG);
                        m_sreg |= (EQSPIF_WIP_FLAG);
                        m_sreg |= (EQSPIF_WIP_FLAG);
                        // Should I be checking the lock register(s) here?
                        // Should I be checking the lock register(s) here?
                        for(int i=0; i<MEMBYTES; i++)
                        for(unsigned i=0; i<m_membytes; i++)
                                m_mem[i] = 0x0ff;
                                m_mem[i] = 0x0ff;
                } else if (m_state == EQSPIF_PROGRAM_OTP) {
                } else if (m_state == EQSPIF_PROGRAM_OTP) {
                        // Program the One-Time Programmable (OTP memory
                        // Program the One-Time Programmable (OTP memory
                        if (m_debug) printf("EQSPI: OTP Program write cycle begins\n");
                        if (m_debug) printf("EQSPI: OTP Program write cycle begins\n");
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
                        if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
Line 261... Line 274...
                        m_state = EQSPIF_IDLE;
                        m_state = EQSPIF_IDLE;
                } else if (m_state == EQSPIF_RELEASE) {
                } else if (m_state == EQSPIF_RELEASE) {
                        m_write_count = tRES;
                        m_write_count = tRES;
                        m_state = EQSPIF_IDLE;
                        m_state = EQSPIF_IDLE;
                */
                */
                } else if (m_state == EQSPIF_QUAD_READ_CMD) {
 
                        m_state = EQSPIF_IDLE;
 
                        if (m_mode_byte!=0)
 
                                m_quad_mode = false;
 
                        else
 
                                m_state = EQSPIF_XIP;
 
                } else if (m_state == EQSPIF_QUAD_READ) {
                } else if (m_state == EQSPIF_QUAD_READ) {
                        m_state = EQSPIF_IDLE;
                        m_state = EQSPIF_IDLE;
                        if (m_mode_byte!=0)
                        if (m_mode_byte!=0)
                                m_quad_mode = false;
                                m_quad_mode = EQSPIF_QMODE_SPI;
                        else
                        else {
 
                                if (m_quad_mode == EQSPIF_QMODE_SPI_ADDR)
 
                                        m_quad_mode = EQSPIF_QMODE_SPI;
                                m_state = EQSPIF_XIP;
                                m_state = EQSPIF_XIP;
                // } else if (m_state == EQSPIF_XIP) {
                        }
                }
                }
 
 
                m_oreg = 0x0fe;
                m_oreg = 0x0fe;
                m_count= 0;
                m_count= 0;
                int out = m_nxtout[3];
                int out = m_nxtout[3];
Line 320... Line 329...
        if (m_state == EQSPIF_XIP) {
        if (m_state == EQSPIF_XIP) {
                assert(m_quad_mode);
                assert(m_quad_mode);
                if (m_count == 24) {
                if (m_count == 24) {
                        if (m_debug) printf("EQSPI: Entering from Quad-Read Idle to Quad-Read\n");
                        if (m_debug) printf("EQSPI: Entering from Quad-Read Idle to Quad-Read\n");
                        if (m_debug) printf("EQSPI: QI/O Idle Addr = %02x\n", m_ireg&0x0ffffff);
                        if (m_debug) printf("EQSPI: QI/O Idle Addr = %02x\n", m_ireg&0x0ffffff);
                        m_addr = (m_ireg) & 0x0ffffff;
                        m_addr = (m_ireg) & m_memmask;
                        assert((m_addr & 0xfc00000)==0);
                        assert((m_addr & (~(m_memmask)))==0);
 
                } else if (m_count == 24 + 4*8) {// After the idle bits
                        m_state = EQSPIF_QUAD_READ;
                        m_state = EQSPIF_QUAD_READ;
 
                        if (m_debug) printf("EQSPI: QI/O Dummy = %04x\n", m_ireg);
 
                        m_mode_byte = (m_ireg>>24) & 0x10;
                } m_oreg = 0;
                } m_oreg = 0;
        } else if (m_count == 8) {
        } else if (m_count == 8) {
                QOREG(0x0a5);
                QOREG(0x0a5);
                // printf("SFLASH-CMD = %02x\n", m_ireg & 0x0ff);
                // printf("SFLASH-CMD = %02x\n", m_ireg & 0x0ff);
                // Figure out what command we've been given
                // Figure out what command we've been given
Line 375... Line 387...
                case 0x20: // Subsector Erase
                case 0x20: // Subsector Erase
                        if (2 != (m_sreg & 0x203)) {
                        if (2 != (m_sreg & 0x203)) {
                                if (m_debug) printf("EQSPI: WEL not set, cannot do a subsector erase\n");
                                if (m_debug) printf("EQSPI: WEL not set, cannot do a subsector erase\n");
                                m_state = EQSPIF_INVALID;
                                m_state = EQSPIF_INVALID;
                                assert(0&&"WEL not set");
                                assert(0&&"WEL not set");
                        } else
                        } else {
                                m_state = EQSPIF_SUBSECTOR_ERASE;
                                m_state = EQSPIF_SUBSECTOR_ERASE;
 
                                if (m_debug) printf("EQSPI: SUBSECTOR_ERASE COMMAND\n");
 
                        }
                        break;
                        break;
                case 0x32: // QUAD Page program, 4 bits at a time
                case 0x32: // QUAD Page program, 4 bits at a time
                        if (2 != (m_sreg & 0x203)) {
                        if (2 != (m_sreg & 0x203)) {
                                if (m_debug) printf("EQSPI: Cannot program at this time, SREG = %x\n", m_sreg);
                                if (m_debug) printf("EQSPI: Cannot program at this time, SREG = %x\n", m_sreg);
                                m_state = EQSPIF_INVALID;
                                m_state = EQSPIF_INVALID;
Line 419... Line 433...
                        m_state = EQSPIF_RDEVCONFIG;
                        m_state = EQSPIF_RDEVCONFIG;
                        if (m_debug) printf("EQSPI: READING EVCONFIG REGISTER: %02x\n", m_evconfig);
                        if (m_debug) printf("EQSPI: READING EVCONFIG REGISTER: %02x\n", m_evconfig);
                        QOREG(m_evconfig);
                        QOREG(m_evconfig);
                        break;
                        break;
                case 0x06b:
                case 0x06b:
                        m_state = EQSPIF_QUAD_READ_CMD;
                        m_state = EQSPIF_QUAD_OREAD_CMD;
                        // m_quad_mode = true; // Not yet, need to wait past dummy registers
                        // m_quad_mode = true; // Not yet, need to wait past dummy registers
                        break;
                        break;
                case 0x70: // Read flag status register
                case 0x70: // Read flag status register
                        m_state = EQSPIF_RDFLAGS;
                        m_state = EQSPIF_RDFLAGS;
                        if (m_debug) printf("EQSPI: READING FLAGSTATUS REGISTER: %02x\n", m_flagreg);
                        if (m_debug) printf("EQSPI: READING FLAGSTATUS REGISTER: %02x\n", m_flagreg);
Line 477... Line 491...
                case 0xe8: // Read lock register
                case 0xe8: // Read lock register
                        m_state = EQSPIF_RDLOCK;
                        m_state = EQSPIF_RDLOCK;
                        if (m_debug) printf("EQSPI: READ LOCK REGISTER (Waiting on address)\n");
                        if (m_debug) printf("EQSPI: READ LOCK REGISTER (Waiting on address)\n");
                        break;
                        break;
                case 0x0eb: // Here's the (other) read that we support
                case 0x0eb: // Here's the (other) read that we support
                        // printf("EQSPI: QUAD-I/O-READ\n");
                        m_state = EQSPIF_QUAD_IOREAD_CMD;
                        // m_state = EQSPIF_QUAD_READ_CMD;
                        m_quad_mode = EQSPIF_QMODE_QSPI_ADDR;
                        // m_quad_mode = true;
 
                        assert(0 && "Quad Input/Output fast read not supported");
 
                        break;
                        break;
                default:
                default:
                        printf("EQSPI: UNRECOGNIZED SPI FLASH CMD: %02x\n", m_ireg&0x0ff);
                        printf("EQSPI: UNRECOGNIZED SPI FLASH CMD: %02x\n", m_ireg&0x0ff);
                        m_state = EQSPIF_INVALID;
                        m_state = EQSPIF_INVALID;
                        assert(0 && "Unrecognized command\n");
                        assert(0 && "Unrecognized command\n");
Line 506... Line 518...
                                exit(-2);
                                exit(-2);
                                m_state = EQSPIF_IDLE;
                                m_state = EQSPIF_IDLE;
                        }
                        }
                        break;
                        break;
                case EQSPIF_WRCR: // Write volatile config register, 0x81
                case EQSPIF_WRCR: // Write volatile config register, 0x81
                        if (m_count == 8+8) {
                        if (m_count == 8+8+8) {
                                m_vconfig = m_ireg & 0x0ff;
                                m_vconfig = m_ireg & 0x0ff;
                                printf("Setting volatile config register to %08x\n", m_vconfig);
                                if (m_debug) printf("Setting volatile config register to %08x\n", m_vconfig);
                                assert((m_vconfig & 0xfb)==0x8b);
                                assert((m_vconfig & 0xfb)==0x8b);
                        } break;
                        } break;
                case EQSPIF_WRNVCONFIG: // Write nonvolatile config register
                case EQSPIF_WRNVCONFIG: // Write nonvolatile config register
                        if (m_count == 8+8) {
                        if (m_count == 8+8+8) {
                                m_nvconfig = m_ireg & 0x0ffdf;
                                m_nvconfig = m_ireg & 0x0ffdf;
                                printf("Setting nonvolatile config register to %08x\n", m_nvconfig);
                                if (m_debug) printf("Setting nonvolatile config register to %08x\n", m_nvconfig);
                                assert((m_nvconfig & 0xffc5)==0x8fc5);
                                assert((m_nvconfig & 0xffc5)==0x8fc5);
                        } break;
                        } break;
                case EQSPIF_WREVCONFIG: // Write enhanced volatile config reg
                case EQSPIF_WREVCONFIG: // Write enhanced volatile config reg
                        if (m_count == 8+8) {
                        if (m_count == 8+8) {
                                m_evconfig = m_ireg & 0x0ff;
                                m_evconfig = m_ireg & 0x0ff;
                                printf("Setting enhanced volatile config register to %08x\n", m_evconfig);
                                if (m_debug) printf("Setting enhanced volatile config register to %08x\n", m_evconfig);
                                assert((m_evconfig & 0x0d7)==0xd7);
                                assert((m_evconfig & 0x0d7)==0xd7);
                        } break;
                        } break;
                case EQSPIF_WRLOCK:
                case EQSPIF_WRLOCK:
                        if (m_count == 32) {
                        if (m_count == 32) {
                                m_addr = (m_ireg>>24)&0x0ff;
                                m_addr = (m_ireg>>24)&0x0ff;
                                if ((m_lockregs[m_addr]&2)==0)
                                if ((m_lockregs[m_addr]&2)==0)
                                        m_lockregs[m_addr] = m_ireg&3;
                                        m_lockregs[m_addr] = m_ireg&3;
                                printf("Setting lock register[%02x] to %d\n", m_addr, m_lockregs[m_addr]);
                                if (m_debug) printf("Setting lock register[%02x] to %d\n", m_addr, m_lockregs[m_addr]);
                                assert((m_config & 0xfb)==0x8b);
 
                        } break;
                        } break;
                case EQSPIF_RDLOCK:
                case EQSPIF_RDLOCK:
                        if (m_count == 24) {
                        if (m_count == 24) {
                                m_addr = (m_ireg>>16)&0x0ff;
                                m_addr = (m_ireg>>16)&0x0ff;
                                QOREG(m_lockregs[m_addr]);
                                QOREG(m_lockregs[m_addr]);
                                printf("Reading lock register[%02x]: %d\n", m_addr, m_lockregs[m_addr]);
                                if (m_debug) printf("Reading lock register[%02x]: %d\n", m_addr, m_lockregs[m_addr]);
                        } else
                        } else
                                QOREG(m_lockregs[m_addr]);
                                QOREG(m_lockregs[m_addr]);
                        break;
                        break;
                case EQSPIF_CLRFLAGS:
                case EQSPIF_CLRFLAGS:
                        assert(0 && "Too many clocks for CLSR command!!\n");
                        assert(0 && "Too many clocks for CLSR command!!\n");
Line 595... Line 606...
                        if (m_debug) printf("Read VCONF = %02x\n", m_vconfig);
                        if (m_debug) printf("Read VCONF = %02x\n", m_vconfig);
                        QOREG(m_creg);
                        QOREG(m_creg);
                        break;
                        break;
                case EQSPIF_FAST_READ:
                case EQSPIF_FAST_READ:
                        if (m_count < 32) {
                        if (m_count < 32) {
                                if (m_debug) printf("FAST READ, WAITING FOR FULL COMMAND (count = %d)\n", m_count);
 
                                QOREG(0x0c3);
                                QOREG(0x0c3);
                        } else if (m_count == 32) {
                        } else if (m_count == 32) {
                                m_addr = m_ireg & 0x0ffffff;
                                m_addr = m_ireg & m_memmask;
                                if (m_debug) printf("FAST READ, ADDR = %08x\n", m_addr);
                                if (m_debug) printf("FAST READ, ADDR = %08x\n", m_addr);
                                QOREG(0x0c3);
                                QOREG(0x0c3);
                                assert((m_addr & 0xf000003)==0);
                                if (m_addr & (~(m_memmask))) {
 
                                        printf("EQSPI: ADDR = %08x ? !!\n", m_addr);
 
                                } assert((m_addr & (~(m_memmask)))==0);
                        } else if ((m_count >= 40)&&(0 == (m_sreg&0x01))) {
                        } else if ((m_count >= 40)&&(0 == (m_sreg&0x01))) {
                                if (m_count == 40)
                                if ((m_debug)&&(m_count == 40))
                                        printf("DUMMY BYTE COMPLETE ...\n");
                                        printf("DUMMY BYTE COMPLETE ...\n");
                                QOREG(m_mem[m_addr++]);
                                QOREG(m_mem[m_addr++]);
                                if (m_debug) printf("SPIF[%08x] = %02x -> %02x\n", m_addr-1, m_mem[m_addr-1]&0x0ff, m_oreg);
                                if (m_debug) printf("SPIF[%08x] = %02x -> %02x\n", m_addr-1, m_mem[m_addr-1]&0x0ff, m_oreg);
                        } else if (0 != (m_sreg&0x01)) {
                        } else if (0 != (m_sreg&0x01)) {
                                m_oreg = 0;
                                m_oreg = 0;
                                if (m_debug) printf("CANNOT READ WHEN WRITE IN PROGRESS, m_sreg = %02x\n", m_sreg);
                                if (m_debug) printf("CANNOT READ WHEN WRITE IN PROGRESS, m_sreg = %02x\n", m_sreg);
                        } else printf("How did I get here, m_count = %d\n", m_count);
                        } else printf("How did I get here, m_count = %d\n", m_count);
                        break;
                        break;
                case EQSPIF_QUAD_READ_CMD:
                case EQSPIF_QUAD_IOREAD_CMD:
                        // The command to go into quad read mode took 8 bits
 
                        // that changes the timings, else we'd use quad_Read
 
                        // below
 
                        if (m_count == 32) {
                        if (m_count == 32) {
                                m_addr = m_ireg & 0x0ffffff;
                                m_addr = m_ireg & m_memmask;
                                // printf("FAST READ, ADDR = %08x\n", m_addr);
                                if (m_debug) printf("EQSPI: QUAD I/O READ, ADDR = %06x (%02x:%02x:%02x:%02x)\n", m_addr,
                                printf("EQSPI: QUAD READ, ADDR = %06x (%02x:%02x:%02x:%02x)\n", m_addr,
 
                                        (m_addr<0x1000000)?(m_mem[m_addr]&0x0ff):0,
                                        (m_addr<0x1000000)?(m_mem[m_addr]&0x0ff):0,
                                        (m_addr<0x0ffffff)?(m_mem[m_addr+1]&0x0ff):0,
                                        (m_addr<0x0ffffff)?(m_mem[m_addr+1]&0x0ff):0,
                                        (m_addr<0x0fffffe)?(m_mem[m_addr+2]&0x0ff):0,
                                        (m_addr<0x0fffffe)?(m_mem[m_addr+2]&0x0ff):0,
                                        (m_addr<0x0fffffd)?(m_mem[m_addr+3]&0x0ff):0);
                                        (m_addr<0x0fffffd)?(m_mem[m_addr+3]&0x0ff):0);
                                assert((m_addr & (~(MEMBYTES-1)))==0);
                                assert((m_addr & (~(m_memmask)))==0);
                        } else if (m_count == 32+8) {
                        } else if (m_count == 8+24+8*4) {
                                QOREG(m_mem[m_addr++]);
                                QOREG(m_mem[m_addr++]);
                                m_quad_mode = true;
                                m_quad_mode = EQSPIF_QMODE_QSPI_ADDR;
                                m_mode_byte = (m_ireg & 0x080);
                                m_mode_byte = (m_ireg & 0x080);
                                printf("EQSPI: (QUAD) MODE BYTE = %02x\n", m_mode_byte);
                                m_state = EQSPIF_QUAD_READ;
                        } else if ((m_count > 32+8)&&(0 == (m_sreg&0x01))) {
 
                                QOREG(m_mem[m_addr++]);
 
                                // printf("EQSPIF[%08x]/QR = %02x\n",
 
                                        // m_addr-1, m_oreg);
 
                        } else {
                        } else {
                                // printf("ERR: EQSPIF--TRYING TO READ WHILE BUSY! (count = %d)\n", m_count);
 
                                m_oreg = 0;
                                m_oreg = 0;
                        }
                        }
                        break;
                        break;
 
                case EQSPIF_QUAD_OREAD_CMD:
 
                        if (m_count == 8+24) {
 
                                m_addr = m_ireg & m_memmask;
 
                                // printf("FAST READ, ADDR = %08x\n", m_addr);
 
                                if (m_debug) printf("EQSPI: QUAD READ, ADDR = %06x (%02x:%02x:%02x:%02x)\n", m_addr,
 
                                        (m_addr<0x1000000)?(m_mem[m_addr]&0x0ff):0,
 
                                        (m_addr<0x0ffffff)?(m_mem[m_addr+1]&0x0ff):0,
 
                                        (m_addr<0x0fffffe)?(m_mem[m_addr+2]&0x0ff):0,
 
                                        (m_addr<0x0fffffd)?(m_mem[m_addr+3]&0x0ff):0);
 
                                assert((m_addr & (~(m_memmask)))==0);
 
                        } else if (m_count == 8+24+4*8) {
 
                                QOREG(m_mem[m_addr]);
 
                                m_quad_mode = EQSPIF_QMODE_SPI_ADDR;
 
                                m_mode_byte = (m_ireg & 0x080);
 
                                if (m_debug) printf("EQSPI: (QUAD) MODE BYTE = %02x\n", m_mode_byte);
 
                                m_state = EQSPIF_QUAD_READ;
 
                        }
 
                        break;
                case EQSPIF_QUAD_READ:
                case EQSPIF_QUAD_READ:
                        if (m_count == 24+8*4) {// Requires 8 QUAD clocks
                        if ((m_count >= 64)&&(0 == (m_sreg&0x01))) {
                                m_mode_byte = (m_ireg>>24) & 0x10;
 
                                printf("EQSPI/QR: MODE BYTE = %02x\n", m_mode_byte);
 
                                QOREG(m_mem[m_addr++]);
                                QOREG(m_mem[m_addr++]);
                        } else if ((m_count >= 64)&&(0 == (m_sreg&0x01))) {
                                // printf("EQSPIF[%08x]/QR = %02x\n", m_addr-1, m_oreg & 0x0ff);
                                QOREG(m_mem[m_addr++]);
 
                                printf("EQSPIF[%08x]/QR = %02x\n", m_addr-1, m_oreg & 0x0ff);
 
                        } else {
                        } else {
                                m_oreg = 0;
                                m_oreg = 0;
                                printf("EQSPI/QR ... m_count = %d\n", m_count);
                                if (m_debug) printf("EQSPI/QR ... m_count = %d\n", m_count);
                        }
                        }
                        break;
                        break;
                case EQSPIF_PP:
                case EQSPIF_PP:
                        if (m_count == 32) {
                        if (m_count == 32) {
                                m_addr = m_ireg & 0x0ffffff;
                                m_addr = m_ireg & m_memmask;
                                if (m_debug) printf("EQSPI: PAGE-PROGRAM ADDR = %06x\n", m_addr);
                                if (m_debug) printf("EQSPI: PAGE-PROGRAM ADDR = %06x\n", m_addr);
                                assert((m_addr & 0xfc00000)==0);
                                assert((m_addr & (~(m_memmask)))==0);
                                // m_page = m_addr >> 8;
                                // m_page = m_addr >> 8;
                                for(int i=0; i<256; i++)
                                for(int i=0; i<256; i++)
                                        m_pmem[i] = 0x0ff;
                                        m_pmem[i] = 0x0ff;
                        } else if (m_count >= 40) {
                        } else if (m_count >= 40) {
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
                                // printf("EQSPI: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
                                // printf("EQSPI: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
                        } break;
                        } break;
                case EQSPIF_QPP:
                case EQSPIF_QPP:
                        if (m_count == 32) {
                        if (m_count == 32) {
                                m_addr = m_ireg & 0x0ffffff;
                                m_addr = m_ireg & m_memmask;
                                m_quad_mode = true;
                                m_quad_mode = EQSPIF_QMODE_SPI_ADDR;
                                if (m_debug) printf("EQSPI/QR: PAGE-PROGRAM ADDR = %06x\n", m_addr);
                                if (m_debug) printf("EQSPI/QR: PAGE-PROGRAM ADDR = %06x\n", m_addr);
                                assert((m_addr & 0xfc00000)==0);
                                assert((m_addr & (~(m_memmask)))==0);
                                // m_page = m_addr >> 8;
 
                                for(int i=0; i<256; i++)
                                for(int i=0; i<256; i++)
                                        m_pmem[i] = 0x0ff;
                                        m_pmem[i] = 0x0ff;
                        } else if (m_count >= 40) {
                        } else if (m_count >= 40) {
 
                                if (m_debug) printf("EQSPI: PROGRAM[%06x] = %02x\n", m_addr, m_ireg & 0x0ff);
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
                                m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
                                // printf("EQSPI/QR: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
 
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
                                m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
                        } break;
                        } break;
                case EQSPIF_SUBSECTOR_ERASE:
                case EQSPIF_SUBSECTOR_ERASE:
                        if (m_count == 32) {
                        if (m_count == 32) {
                                m_addr = m_ireg & 0x0fff000;
                                m_addr = m_ireg & 0x0fff000;

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