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%% together with this PDF file and a copy of the GPL-3.0 license
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%% together with this PDF file and a copy of the GPL-3.0 license
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%% this file is distributed under.
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%% this file is distributed under.
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%%
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%%
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%%
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%%
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%% Creator: Dan Gisselquist
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%% Creator: Dan Gisselquist
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%% Gisselquist Tecnology, LLC
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%% Gisselquist Technology, LLC
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%%
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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%%
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%%
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\documentclass{gqtekspec}
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\documentclass{gqtekspec}
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\project{Quad SPI Flash Controller}
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\project{Quad SPI Flash Controller}
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\title{Specification}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq\at opencores.org}
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\email{dgisselq\at opencores.org}
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\revision{Rev.~0.1}
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\revision{Rev.~0.2}
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\begin{document}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\pagestyle{gqtekspecplain}
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\titlepage
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\titlepage
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\begin{license}
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
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with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
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copy.
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copy.
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\end{license}
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\end{license}
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\begin{revisionhistory}
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\begin{revisionhistory}
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0.2 & 5/26/2015 & Gisselquist & Minor spelling changes\\\hline
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0.1 & 5/13/2015 & Gisselquist & First Draft \\\hline
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0.1 & 5/13/2015 & Gisselquist & First Draft \\\hline
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\end{revisionhistory}
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\end{revisionhistory}
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% Revision History
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% Revision History
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% Table of Contents, named Contents
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% Table of Contents, named Contents
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\tableofcontents
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\tableofcontents
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\begin{center}
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\begin{center}
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\begin{wishboneds}
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\begin{wishboneds}
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Revision level of wishbone & WB B4 spec \\\hline
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Revision level of wishbone & WB B4 spec \\\hline
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Type of interface & Slave, (Block) Read/Write \\\hline
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Type of interface & Slave, (Block) Read/Write \\\hline
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Port size & 32--bit \\\hline
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Port size & 32--bit \\\hline
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Port granulity & 32--bit \\\hline
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Port granularity & 32--bit \\\hline
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Maximum Operand Size & 32--bit \\\hline
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Maximum Operand Size & 32--bit \\\hline
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Data transfer ordering & Little Endian \\\hline
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Data transfer ordering & Little Endian \\\hline
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Clock constraints & Must be 100~MHz or slower \\\hline
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Clock constraints & Must be 100~MHz or slower \\\hline
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Signal Names & \begin{tabular}{ll}
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Signal Names & \begin{tabular}{ll}
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Signal Name & Wishbone Equivalent \\\hline
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Signal Name & Wishbone Equivalent \\\hline
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{\tt i\_clk\_100mhz} & {\tt CLK\_I} \\
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{\tt i\_clk\_100mhz} & {\tt CLK\_I} \\
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{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
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{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
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{\tt i\_wb\_ctrl\_stb} & {\tt STB\_I} \\
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{\tt i\_wb\_ctrl\_stb} & {\tt STB\_I} \\
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{\tt i\_wb\_data\_stb} & {\tt STB\_I} \\
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{\tt i\_wb\_data\_stb} & {\tt STB\_I} \\
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{\tt i\_wb\_we} & {\tt WE\_I} \\
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{\tt i\_wb\_we} & {\tt WE\_I} \\
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{\tt i\_wb\_addr} & {\tt ADR\_I} \\
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{\tt i\_wb\_data} & {\tt DAT\_I} \\
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{\tt i\_wb\_data} & {\tt DAT\_I} \\
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{\tt o\_wb\_ack} & {\tt ACK\_O} \\
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{\tt o\_wb\_ack} & {\tt ACK\_O} \\
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{\tt o\_wb\_stall} & {\tt STALL\_O} \\
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{\tt o\_wb\_stall} & {\tt STALL\_O} \\
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{\tt o\_wb\_data} & {\tt DAT\_O}
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{\tt o\_wb\_data} & {\tt DAT\_O}
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\end{tabular}\\\hline
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\end{tabular}\\\hline
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