| Line 1... |
Line 1... |
////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: eqspiflash.v
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// Filename: eqspiflash.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: Wishbone Controlled Quad SPI Flash Controller
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//
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//
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// Purpose: Provide access to the flash device on an Arty, via the Extended
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// Purpose: Provide access to the flash device on an Arty, via the Extended
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// SPI interface. Reads and writes will use the QuadSPI interface
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// SPI interface. Reads and writes will use the QuadSPI interface
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// (4-bits at a time) all other commands (register and otherwise) will use
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// (4-bits at a time) all other commands (register and otherwise) will use
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// the SPI interface (1 bit at a time).
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// the SPI interface (1 bit at a time).
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| Line 88... |
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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| Line 100... |
Line 100... |
//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// `define QSPI_READ_ONLY
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// `define QSPI_READ_ONLY
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module eqspiflash(i_clk_200mhz, i_rst,
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module eqspiflash(i_clk_82mhz, i_rst,
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// Incoming wishbone connection(s)
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// Incoming wishbone connection(s)
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// The two strobe lines allow the data to live on a
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// The two strobe lines allow the data to live on a
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// separate part of the master bus from the control
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// separate part of the master bus from the control
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// registers. Only one strobe will ever be active at any
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// registers. Only one strobe will ever be active at any
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// time, no strobes will ever be active unless i_wb_cyc
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// time, no strobes will ever be active unless i_wb_cyc
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| Line 118... |
Line 118... |
// Interrupt the CPU
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// Interrupt the CPU
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o_interrupt, o_cmd_accepted,
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o_interrupt, o_cmd_accepted,
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// Debug the interface
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// Debug the interface
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o_dbg);
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o_dbg);
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|
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input i_clk_200mhz, i_rst;
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input i_clk_82mhz, i_rst;
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// Wishbone bus inputs
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// Wishbone bus inputs
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input [21:0] i_wb_addr; // 24 bits of addr space
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input [21:0] i_wb_addr; // 24 bits of addr space
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// Wishbone bus outputs
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// Wishbone bus outputs
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| Line 140... |
Line 140... |
output reg o_cmd_accepted;
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output reg o_cmd_accepted;
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//
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//
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output wire [31:0] o_dbg;
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output wire [31:0] o_dbg;
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|
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initial o_cmd_accepted = 1'b0;
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initial o_cmd_accepted = 1'b0;
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always @(posedge i_clk_200mhz)
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always @(posedge i_clk_82mhz)
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o_cmd_accepted=((i_wb_data_stb)||(i_wb_ctrl_stb))&&(~o_wb_stall);
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o_cmd_accepted=((i_wb_data_stb)||(i_wb_ctrl_stb))&&(~o_wb_stall);
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//
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//
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// lleqspi
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// lleqspi
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//
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//
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// Providing the low-level SPI interface
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// Providing the low-level SPI interface
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| Line 152... |
Line 152... |
reg spi_wr, spi_hold, spi_spd, spi_dir, spi_recycle;
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reg spi_wr, spi_hold, spi_spd, spi_dir, spi_recycle;
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reg [31:0] spi_word;
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reg [31:0] spi_word;
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reg [1:0] spi_len;
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reg [1:0] spi_len;
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wire [31:0] spi_out;
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wire [31:0] spi_out;
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wire spi_valid, spi_busy, spi_stopped;
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wire spi_valid, spi_busy, spi_stopped;
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lleqspi lowlvl(i_clk_200mhz, spi_wr, spi_hold, spi_word, spi_len,
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lleqspi lowlvl(i_clk_82mhz, spi_wr, spi_hold, spi_word, spi_len,
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spi_spd, spi_dir, spi_recycle, spi_out, spi_valid, spi_busy,
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spi_spd, spi_dir, spi_recycle, spi_out, spi_valid, spi_busy,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat);
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat);
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assign spi_stopped = (o_qspi_cs_n)&&(~spi_busy)&&(~spi_wr);
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assign spi_stopped = (o_qspi_cs_n)&&(~spi_busy)&&(~spi_wr);
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|
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| Line 179... |
Line 179... |
bus_pipewr, bus_endwr, bus_ctreq, bus_idreq,
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bus_pipewr, bus_endwr, bus_ctreq, bus_idreq,
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bus_other_req,
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bus_other_req,
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// Live parameters
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// Live parameters
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w_xip, w_quad, w_idloaded, w_leave_xip;
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w_xip, w_quad, w_idloaded, w_leave_xip;
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reg bus_wip;
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reg bus_wip;
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qspibus preproc(i_clk_200mhz, i_rst,
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qspibus preproc(i_clk_82mhz, i_rst,
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i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb,
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i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb,
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i_wb_we, i_wb_addr, i_wb_data,
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i_wb_we, i_wb_addr, i_wb_data,
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bus_wb_ack, bus_wb_stall, bus_wb_data,
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bus_wb_ack, bus_wb_stall, bus_wb_data,
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bus_wr, bus_addr, bus_data, bus_sector,
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bus_wr, bus_addr, bus_data, bus_sector,
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bus_readreq, bus_piperd,
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bus_readreq, bus_piperd,
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| Line 209... |
Line 209... |
wire rd_spi_wr, rd_spi_hold, rd_spi_spd, rd_spi_dir,
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wire rd_spi_wr, rd_spi_hold, rd_spi_spd, rd_spi_dir,
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rd_spi_recycle;
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rd_spi_recycle;
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wire [31:0] rd_spi_word;
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wire [31:0] rd_spi_word;
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wire [1:0] rd_spi_len;
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wire [1:0] rd_spi_len;
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//
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//
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readqspi rdproc(i_clk_200mhz, bus_readreq, bus_piperd,
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readqspi rdproc(i_clk_82mhz, bus_readreq, bus_piperd,
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bus_other_req,
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bus_other_req,
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bus_addr, rd_bus_ack,
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bus_addr, rd_bus_ack,
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rd_qspi_req, rd_qspi_grant,
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rd_qspi_req, rd_qspi_grant,
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rd_spi_wr, rd_spi_hold, rd_spi_word, rd_spi_len,
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rd_spi_wr, rd_spi_hold, rd_spi_word, rd_spi_len,
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rd_spi_spd, rd_spi_dir, rd_spi_recycle,
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rd_spi_spd, rd_spi_dir, rd_spi_recycle,
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| Line 239... |
Line 239... |
wire [31:0] ew_spi_word;
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wire [31:0] ew_spi_word;
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wire [1:0] ew_spi_len;
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wire [1:0] ew_spi_len;
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//
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//
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wire w_ew_wip;
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wire w_ew_wip;
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//
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//
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writeqspi ewproc(i_clk_200mhz, bus_wreq,bus_ereq,
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writeqspi ewproc(i_clk_82mhz, bus_wreq,bus_ereq,
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bus_pipewr, bus_endwr,
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bus_pipewr, bus_endwr,
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bus_addr, bus_data,
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bus_addr, bus_data,
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ew_bus_ack, ew_qspi_req, ew_qspi_grant,
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ew_bus_ack, ew_qspi_req, ew_qspi_grant,
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ew_spi_wr, ew_spi_hold, ew_spi_word, ew_spi_len,
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ew_spi_wr, ew_spi_hold, ew_spi_word, ew_spi_len,
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ew_spi_spd, ew_spi_dir,
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ew_spi_spd, ew_spi_dir,
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| Line 266... |
Line 266... |
// SPI control wires
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// SPI control wires
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wire ct_spi_wr, ct_spi_hold, ct_spi_spd, ct_spi_dir;
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wire ct_spi_wr, ct_spi_hold, ct_spi_spd, ct_spi_dir;
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wire [31:0] ct_spi_word;
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wire [31:0] ct_spi_word;
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wire [1:0] ct_spi_len;
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wire [1:0] ct_spi_len;
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//
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//
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ctrlspi ctproc(i_clk_200mhz,
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ctrlspi ctproc(i_clk_82mhz,
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bus_ctreq, bus_wr, bus_addr[3:0], bus_data, bus_sector,
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bus_ctreq, bus_wr, bus_addr[3:0], bus_data, bus_sector,
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ct_qspi_req, ct_grant,
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ct_qspi_req, ct_grant,
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ct_spi_wr, ct_spi_hold, ct_spi_word, ct_spi_len,
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ct_spi_wr, ct_spi_hold, ct_spi_word, ct_spi_len,
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ct_spi_spd, ct_spi_dir,
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ct_spi_spd, ct_spi_dir,
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spi_out, spi_valid, spi_busy, spi_stopped,
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spi_out, spi_valid, spi_busy, spi_stopped,
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| Line 297... |
Line 297... |
wire [31:0] id_spi_word;
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wire [31:0] id_spi_word;
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wire [1:0] id_spi_len;
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wire [1:0] id_spi_len;
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//
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//
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wire w_id_wip;
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wire w_id_wip;
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//
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//
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idotpqspi idotp(i_clk_200mhz, bus_idreq,
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idotpqspi idotp(i_clk_82mhz, bus_idreq,
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bus_wr, bus_pipewr, bus_addr[4:0], bus_data, id_bus_ack,
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bus_wr, bus_pipewr, bus_addr[4:0], bus_data, id_bus_ack,
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id_qspi_req, id_qspi_grant,
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id_qspi_req, id_qspi_grant,
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id_spi_wr, id_spi_hold, id_spi_word, id_spi_len,
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id_spi_wr, id_spi_hold, id_spi_word, id_spi_len,
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id_spi_spd, id_spi_dir,
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id_spi_spd, id_spi_dir,
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spi_out, spi_valid, spi_busy, spi_stopped,
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spi_out, spi_valid, spi_busy, spi_stopped,
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| Line 309... |
Line 309... |
|
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// Arbitrator
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// Arbitrator
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reg owned;
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reg owned;
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reg [1:0] owner;
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reg [1:0] owner;
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initial owned = 1'b0;
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initial owned = 1'b0;
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always @(posedge i_clk_200mhz) // 7 inputs (spi_stopped is the CE)
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always @(posedge i_clk_82mhz) // 7 inputs (spi_stopped is the CE)
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if ((~owned)&&(spi_stopped))
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if ((~owned)&&(spi_stopped))
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begin
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begin
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casez({rd_qspi_req,ew_qspi_req,id_qspi_req,ct_qspi_req})
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casez({rd_qspi_req,ew_qspi_req,id_qspi_req,ct_qspi_req})
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4'b1???: begin owned<= 1'b1; owner <= 2'b00; end
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4'b1???: begin owned<= 1'b1; owner <= 2'b00; end
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4'b01??: begin owned<= 1'b1; owner <= 2'b01; end
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4'b01??: begin owned<= 1'b1; owner <= 2'b01; end
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| Line 336... |
Line 336... |
assign ew_qspi_grant = (owned)&&(owner == 2'b01);
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assign ew_qspi_grant = (owned)&&(owner == 2'b01);
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assign id_qspi_grant = (owned)&&(owner == 2'b10);
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assign id_qspi_grant = (owned)&&(owner == 2'b10);
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assign ct_grant = (owned)&&(owner == 2'b11);
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assign ct_grant = (owned)&&(owner == 2'b11);
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|
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// Module controller
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// Module controller
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always @(posedge i_clk_200mhz)
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always @(posedge i_clk_82mhz)
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case(owner)
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case(owner)
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2'b00: begin
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2'b00: begin
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spi_wr <= (owned)&&(rd_spi_wr);
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spi_wr <= (owned)&&(rd_spi_wr);
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spi_hold <= rd_spi_hold;
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spi_hold <= rd_spi_hold;
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spi_word <= rd_spi_word;
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spi_word <= rd_spi_word;
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| Line 380... |
Line 380... |
|
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reg last_wip;
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reg last_wip;
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initial bus_wip = 1'b0;
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initial bus_wip = 1'b0;
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initial last_wip = 1'b0;
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initial last_wip = 1'b0;
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initial o_interrupt = 1'b0;
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initial o_interrupt = 1'b0;
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always @(posedge i_clk_200mhz)
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always @(posedge i_clk_82mhz)
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begin
|
begin
|
bus_wip <= w_ew_wip || w_id_wip;
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bus_wip <= w_ew_wip || w_id_wip;
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last_wip <= bus_wip;
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last_wip <= bus_wip;
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o_interrupt <= ((~bus_wip)&&(last_wip));
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o_interrupt <= ((~bus_wip)&&(last_wip));
|
end
|
end
|
|
|
|
|
// Now, let's return values onto the wb bus
|
// Now, let's return values onto the wb bus
|
always @(posedge i_clk_200mhz)
|
always @(posedge i_clk_82mhz)
|
begin
|
begin
|
// Ack our internal bus controller. This means the command was
|
// Ack our internal bus controller. This means the command was
|
// accepted, and the bus can go on to looking for the next
|
// accepted, and the bus can go on to looking for the next
|
// command. It controls the i_wb_stall line, just not the
|
// command. It controls the i_wb_stall line, just not the
|
// i_wb_ack line.
|
// i_wb_ack line.
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| Line 449... |
Line 449... |
|
|
|
|
//
|
//
|
reg pending, lcl_wrreq, lcl_ctreq, lcl_ack, ack, wp_err, wp;
|
reg pending, lcl_wrreq, lcl_ctreq, lcl_ack, ack, wp_err, wp;
|
reg lcl_reg;
|
reg lcl_reg;
|
reg [14:0] esector;
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reg [12:0] esector;
|
reg [21:0] next_addr;
|
reg [21:0] next_addr;
|
|
|
|
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reg pipeable;
|
reg pipeable;
|
reg same_page;
|
reg same_page;
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| Line 581... |
Line 581... |
always @(posedge i_clk)
|
always @(posedge i_clk)
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last_wip <= i_wip;
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last_wip <= i_wip;
|
wire new_req;
|
wire new_req;
|
assign new_req = (pending)&&(~last_pending);
|
assign new_req = (pending)&&(~last_pending);
|
|
|
initial esector = 15'h00;
|
initial esector = 13'h00;
|
initial o_wrreq = 1'b0;
|
initial o_wrreq = 1'b0;
|
initial o_erreq = 1'b0;
|
initial o_erreq = 1'b0;
|
initial wp_err = 1'b0;
|
initial wp_err = 1'b0;
|
initial lcl_ack = 1'b0;
|
initial lcl_ack = 1'b0;
|
initial r_other = 1'b0;
|
initial r_other = 1'b0;
|
| Line 611... |
Line 611... |
// Default ACK is always set to zero, unless the following ...
|
// Default ACK is always set to zero, unless the following ...
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
|
|
if (set_sector)
|
if (set_sector)
|
begin
|
begin
|
esector[13:0] <= { o_data[23:14], 4'h0 };
|
esector[11:0] <= { o_data[21:14], 4'h0 };
|
wp <= (o_data[30])&&(new_req)||(wp)&&(~new_req);
|
wp <= (o_data[30])&&(new_req)||(wp)&&(~new_req);
|
esector[14] <= o_data[28]; // Subsector
|
esector[12] <= o_data[28]; // Subsector
|
if (o_data[28])
|
if (o_data[28])
|
begin
|
begin
|
esector[3:0] <= o_data[13:10];
|
esector[3:0] <= o_data[13:10];
|
end
|
end
|
end
|
end
|
| Line 677... |
Line 677... |
end
|
end
|
|
|
end
|
end
|
|
|
|
|
assign o_wb_data[31:0] = { i_wip, ~wp, i_quad, esector[14],
|
assign o_wb_data[31:0] = { i_wip, ~wp, i_quad, esector[12],
|
i_idloaded, wp_err, i_xip, i_spi_stopped,
|
i_idloaded, wp_err, i_xip, i_spi_stopped,
|
esector[13:0], 10'h00 };
|
2'b00, esector[11:0], 10'h00 };
|
assign o_sector = { esector[13:0], 8'h00 }; // 22 bits
|
assign o_sector = { 2'b00, esector[11:0], 8'h00 }; // 22 bits
|
assign o_other = (r_other)||(o_idreq);
|
assign o_other = (r_other)||(o_idreq);
|
|
|
endmodule
|
endmodule
|
|
|
|
|
| Line 696... |
Line 696... |
`define RD_QUAD_DUMMY 4'h5
|
`define RD_QUAD_DUMMY 4'h5
|
`define RD_QUAD_ADDRESS 4'h6
|
`define RD_QUAD_ADDRESS 4'h6
|
`define RD_XIP 4'h7
|
`define RD_XIP 4'h7
|
`define RD_GO_TO_IDLE 4'h8
|
`define RD_GO_TO_IDLE 4'h8
|
`define RD_GO_TO_XIP 4'h9
|
`define RD_GO_TO_XIP 4'h9
|
|
`define RD_IDLE_QUAD_PORT 4'ha
|
|
|
module readqspi(i_clk, i_readreq, i_piperd, i_other_req, i_addr, o_bus_ack,
|
module readqspi(i_clk, i_readreq, i_piperd, i_other_req, i_addr, o_bus_ack,
|
o_qspi_req, i_grant,
|
o_qspi_req, i_grant,
|
o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
|
o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
|
o_spi_spd, o_spi_dir, o_spi_recycle,
|
o_spi_spd, o_spi_dir, o_spi_recycle,
|
| Line 744... |
Line 745... |
invalid_ack_pipe <= { invalid_ack_pipe[2:0], accepted };
|
invalid_ack_pipe <= { invalid_ack_pipe[2:0], accepted };
|
case(rd_state)
|
case(rd_state)
|
`RD_IDLE: begin
|
`RD_IDLE: begin
|
r_requested <= 1'b0;
|
r_requested <= 1'b0;
|
o_qspi_req <= 1'b0;
|
o_qspi_req <= 1'b0;
|
o_spi_word <= { ((i_quad)? 8'h6B: 8'h0b), i_addr, 2'b00 };
|
// 0x0b is a fast read, uses all SPI protocol
|
|
// 0x6b is a Quad output fast read, uses SPI cmd,
|
|
// SPI address, QSPI data
|
|
// 0xeb is a Quad I/O fast read, using SPI cmd,
|
|
// QSPI address and data
|
|
o_spi_word <= { ((i_quad)? 8'hEB: 8'h0b), i_addr, 2'b00 };
|
o_spi_wr <= 1'b0;
|
o_spi_wr <= 1'b0;
|
o_spi_dir <= 1'b0;
|
o_spi_dir <= 1'b0;
|
o_spi_spd <= 1'b0;
|
o_spi_spd <= 1'b0;
|
o_spi_len <= 2'b11;
|
o_spi_len <= (i_quad)? 2'b00 : 2'b11;
|
r_xip <= (i_xip)&&(i_quad);
|
r_xip <= (i_xip)&&(i_quad);
|
r_leave_xip <= 1'b0; // Not in it, so can't leave it
|
r_leave_xip <= 1'b0; // Not in it, so can't leave it
|
r_quad <= i_quad;
|
r_quad <= i_quad;
|
if (i_readreq)
|
if (i_readreq)
|
begin
|
begin
|
| Line 761... |
Line 767... |
end end
|
end end
|
`RD_IDLE_GET_PORT: begin
|
`RD_IDLE_GET_PORT: begin
|
o_spi_wr <= 1'b1; // Write the address
|
o_spi_wr <= 1'b1; // Write the address
|
o_qspi_req <= 1'b1;
|
o_qspi_req <= 1'b1;
|
if (accepted)
|
if (accepted)
|
|
begin
|
|
rd_state <= (r_quad) ? `RD_IDLE_QUAD_PORT : `RD_SLOW_DUMMY;
|
|
o_spi_word[31:8] <= o_spi_word[23:0];
|
|
end end
|
|
`RD_IDLE_QUAD_PORT: begin
|
|
o_spi_wr <= 1'b1; // Write the command
|
|
o_qspi_req <= 1'b1;
|
|
o_spi_spd <= 1'b1;
|
|
o_spi_dir <= 1'b0;
|
|
o_spi_len <= 2'b10;
|
|
|
|
// We haven't saved our address any where but in the
|
|
// SPI word we just sent. Hence, let's just
|
|
// grab it from there.
|
|
if (accepted)
|
rd_state <= `RD_SLOW_DUMMY;
|
rd_state <= `RD_SLOW_DUMMY;
|
end
|
end
|
`RD_SLOW_DUMMY: begin
|
`RD_SLOW_DUMMY: begin
|
o_spi_wr <= 1'b1; // Write 8 dummy clocks
|
o_spi_wr <= 1'b1; // Write 8 dummy clocks--this is the same for
|
o_qspi_req <= 1'b1;
|
o_qspi_req <= 1'b1; // both Quad I/O, Quad O, and fast-read commands
|
o_spi_dir <= 1'b0;
|
o_spi_dir <= 1'b0;
|
o_spi_spd <= 1'b0;
|
o_spi_spd <= r_quad;
|
o_spi_word[31:24] <= (r_xip) ? 8'h00 : 8'hff;
|
o_spi_word[31:0] <= (r_xip) ? 32'h00 : 32'hffffffff;
|
o_spi_len <= 2'b00; // 8 clocks = 8-bits
|
o_spi_len <= (r_quad)? 2'b11:2'b00; // 8 clocks
|
if (accepted)
|
if (accepted)
|
rd_state <= (r_quad)?`RD_QUAD_READ_DATA
|
rd_state <= (r_quad)?`RD_QUAD_READ_DATA
|
: `RD_SLOW_READ_DATA;
|
: `RD_SLOW_READ_DATA;
|
end
|
end
|
`RD_SLOW_READ_DATA: begin
|
`RD_SLOW_READ_DATA: begin
|
