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//
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: llqspi.v
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// Filename: llqspi.v
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//
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//
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// Project: FPGA library development (Basys-3 development board)
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// Project: Wishbone Controlled Quad SPI Flash Controller
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//
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//
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// Purpose: Reads/writes a word (user selectable number of bytes) of data
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// Purpose: Reads/writes a word (user selectable number of bytes) of data
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// to/from a Quad SPI port. The port is understood to be
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// to/from a Quad SPI port. The port is understood to be
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// a normal SPI port unless the driver requests four bit mode.
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// a normal SPI port unless the driver requests four bit mode.
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// When not in use, unlike our previous SPI work, no bits will
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// When not in use, unlike our previous SPI work, no bits will
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// toggle.
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// toggle.
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnology, LLC
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//
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//
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// Copyright: 2015
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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`define QSPI_IDLE 0
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`define QSPI_IDLE 0
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`define QSPI_START 1
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`define QSPI_START 1
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`define QSPI_BITS 2
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`define QSPI_BITS 2
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`define QSPI_READY 3
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`define QSPI_READY 3
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`define QSPI_STOP 4
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`define QSPI_STOP 4
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module llqspi(i_clk,
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module llqspi(i_clk,
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// Module interface
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// Module interface
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i_wr, i_hold, i_word, i_len, i_spd, i_dir,
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i_wr, i_hold, i_word, i_len, i_spd, i_dir,
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o_word, o_valid, o_busy,
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o_word, o_valid, o_busy,
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// QSPI interface
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// QSPI interface
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o_sck, o_cs_n, o_mod, o_dat, i_dat,
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o_sck, o_cs_n, o_mod, o_dat, i_dat);
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// Wbscope interface
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o_dbg);
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input i_clk;
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input i_clk;
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// Chip interface
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// Chip interface
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// Can send info
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// Can send info
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// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
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// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
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// i_word = { 1'b0, 32'info to send },
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// i_word = { 1'b0, 32'info to send },
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output reg o_sck;
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output reg o_sck;
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output reg o_cs_n;
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output reg o_cs_n;
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output reg [1:0] o_mod;
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output reg [1:0] o_mod;
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output reg [3:0] o_dat;
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output reg [3:0] o_dat;
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input [3:0] i_dat;
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input [3:0] i_dat;
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output wire [22:0] o_dbg;
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assign o_dbg = { state, spi_len, // 3+6+ 14
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o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
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// Timing:
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// Timing:
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//
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//
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// Tick Clk BSY/WR CS_n BIT/MO STATE
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// Tick Clk BSY/WR CS_n BIT/MO STATE
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// 0 1 0/0 1 -
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// 0 1 0/0 1 -
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