| Line 35... |
Line 35... |
// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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`define QSPI_IDLE 0
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`define QSPI_IDLE 3'h0
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`define QSPI_START 1
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`define QSPI_START 3'h1
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`define QSPI_BITS 2
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`define QSPI_BITS 3'h2
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`define QSPI_READY 3
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`define QSPI_READY 3'h3
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`define QSPI_STOP 4
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`define QSPI_HOLDING 3'h4
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`define QSPI_STOP_B 5
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`define QSPI_STOP 3'h5
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`define QSPI_STOP_B 3'h6
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// Modes
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// Modes
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`define QSPI_MOD_SPI 2'b00
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`define QSPI_MOD_SPI 2'b00
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`define QSPI_MOD_QOUT 2'b10
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`define QSPI_MOD_QOUT 2'b10
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`define QSPI_MOD_QIN 2'b11
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`define QSPI_MOD_QIN 2'b11
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| Line 264... |
Line 265... |
o_busy <= 1'b1;
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o_busy <= 1'b1;
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// This is the state on the last clock (both low and
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// This is the state on the last clock (both low and
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// high clocks) of the data. Data is valid during
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// high clocks) of the data. Data is valid during
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// this state. Here we chose to either STOP or
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// this state. Here we chose to either STOP or
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// continue and transmit more.
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// continue and transmit more.
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o_sck <= (i_hold); // Stay here on hold, no clocks
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o_sck <= (i_hold); // No clocks while holding
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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begin
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begin
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state <= `QSPI_BITS;
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state <= `QSPI_BITS;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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o_sck <= 1'b0;
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o_sck <= 1'b0;
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| Line 301... |
Line 302... |
end else if (o_mod[1])
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end else if (o_mod[1])
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begin
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begin
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r_input <= { r_input[26:0], i_dat };
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r_input <= { r_input[26:0], i_dat };
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o_word <= { r_input[27:0], i_dat };
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o_word <= { r_input[27:0], i_dat };
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end
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end
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end else if (i_hold)
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begin // Stay here, holding the clock high, if the user
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// has more data, but it isn't ready yet.
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o_busy <= 1'b0;
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end else begin
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end else begin
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o_sck <= 1'b1;
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o_sck <= 1'b1;
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state <= `QSPI_STOP;
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state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
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o_busy <= (~i_hold);
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// Read a bit upon any transition
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// Read a bit upon any transition
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o_valid <= 1'b1;
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o_valid <= 1'b1;
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if (~o_mod[1])
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if (~o_mod[1])
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begin
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begin
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| Line 321... |
Line 319... |
begin
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begin
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r_input <= { r_input[26:0], i_dat };
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r_input <= { r_input[26:0], i_dat };
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o_word <= { r_input[27:0], i_dat };
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o_word <= { r_input[27:0], i_dat };
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end
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end
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end
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end
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end else if (state == `QSPI_HOLDING)
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begin
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// We need this state so that the o_valid signal
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// can get strobed with our last result. Otherwise
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// we could just sit in READY waiting for a new command.
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//
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// Incidentally, the change producing this state was
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// the result of a nasty race condition. See the
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// commends in wbqspiflash for more details.
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//
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o_valid <= 1'b0;
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o_cs_n <= 1'b0;
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o_busy <= 1'b0;
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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begin
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state <= `QSPI_BITS;
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o_busy <= 1'b1;
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o_sck <= 1'b0;
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// Read the new request off the bus
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r_spd <= i_spd;
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r_dir <= i_dir;
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// Set up the first bits on the bus
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o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
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if (i_spd)
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begin
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o_dat <= i_word[31:28];
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r_word <= { i_word[27:0], 4'h0 };
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spi_len<= { 1'b0, i_len, 3'b100 };
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end else begin
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o_dat <= { 3'b110, i_word[31] };
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r_word <= { i_word[30:0], 1'b0 };
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spi_len<= { 1'b0, i_len, 3'b111 };
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end
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end else begin
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o_sck <= 1'b1;
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state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
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o_busy <= (~i_hold);
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end
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end else if (state == `QSPI_STOP)
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end else if (state == `QSPI_STOP)
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begin
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begin
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o_sck <= 1'b1; // Stop the clock
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o_sck <= 1'b1; // Stop the clock
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o_valid <= 1'b0; // Output may have just been valid, but no more
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o_valid <= 1'b0; // Output may have just been valid, but no more
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o_busy <= 1'b1; // Still busy till port is clear
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o_busy <= 1'b1; // Still busy till port is clear
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