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//
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbspiflash.v
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// Filename: wbspiflash.v
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//
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//
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// Project: FPGA library development (Basys3 development board)
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// Project: Wishbone Controlled Quad SPI Flash Controller
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//
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//
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// Purpose: Access a Quad SPI flash via a WISHBONE interface. This
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// Purpose: Access a Quad SPI flash via a WISHBONE interface. This
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// includes both read and write (and erase) commands to the SPI
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// includes both read and write (and erase) commands to the SPI
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// flash. All read/write commands are accomplished using the
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// flash. All read/write commands are accomplished using the
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// high speed (4-bit) interface. Further, the device will be
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// high speed (4-bit) interface. Further, the device will be
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// left/kept in the 4-bit read interface mode between accesses,
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// left/kept in the 4-bit read interface mode between accesses,
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// for a minimum read latency.
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// for a minimum read latency.
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//
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//
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// Wishbone Registers (See Basys3 Wishbone HTML page):
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// Wishbone Registers (See spec sheet for more detail):
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// 0: local config(r) / erase commands(w) / deep power down cmds / etc.
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// 0: local config(r) / erase commands(w) / deep power down cmds / etc.
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// R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
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// R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
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// { last_erased_sector, 14'h00 } if (WIP)
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// { last_erased_sector, 14'h00 } if (WIP)
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// else { current_sector_being_erased, 14'h00 }
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// else { current_sector_being_erased, 14'h00 }
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// current if write in progress, last if written
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// current if write in progress, last if written
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// W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
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// W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
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// 1: Read ID (read only)
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// 1: Configuration register
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// 2: Status register (R(/w?)), reads update the WIP bit ...
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// 2: Status register (R/w)
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// 3: Read ID (read only)
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// (19 bits): Data (R/w, but expect writes to take a while)
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// (19 bits): Data (R/w, but expect writes to take a while)
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//
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//
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnology, LLC
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//
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//
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// Copyright: 2015
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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`define WBQSPI_RESET 0
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`define WBQSPI_RESET 0
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`define WBQSPI_RESET_WEN 1
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`define WBQSPI_RESET_WEN 1
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`define WBQSPI_IDLE 2
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`define WBQSPI_IDLE 2
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`define WBQSPI_RDIDLE 3 // Idle, but in fast read mode
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`define WBQSPI_RDIDLE 3 // Idle, but in fast read mode
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`define WBQSPI_WBDECODE 4
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`define WBQSPI_WBDECODE 4
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i_wb_addr, i_wb_data,
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i_wb_addr, i_wb_data,
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// Wishbone return values
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// Wishbone return values
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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// Quad Spi connections to the external device
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// Quad Spi connections to the external device
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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o_interrupt,
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o_interrupt);
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// Info for a wbscope
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o_debug);
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input i_clk_100mhz;
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input i_clk_100mhz;
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// Wishbone, inputs first
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// Wishbone, inputs first
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input [19:0] i_wb_addr;
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input [19:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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output wire [1:0] o_qspi_mod;
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output wire [1:0] o_qspi_mod;
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output wire [3:0] o_qspi_dat;
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output wire [3:0] o_qspi_dat;
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input [3:0] i_qspi_dat;
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input [3:0] i_qspi_dat;
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// Interrupt line
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// Interrupt line
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output reg o_interrupt;
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output reg o_interrupt;
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// Debug/scope
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output wire [31:0] o_debug;
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reg spi_wr, spi_hold, spi_spd, spi_dir;
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reg spi_wr, spi_hold, spi_spd, spi_dir;
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reg [31:0] spi_in;
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reg [31:0] spi_in;
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reg [1:0] spi_len;
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reg [1:0] spi_len;
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wire [31:0] spi_out;
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wire [31:0] spi_out;
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wire spi_valid, spi_busy;
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wire spi_valid, spi_busy;
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wire [22:0] spi_dbg;
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llqspi lldriver(i_clk_100mhz,
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llqspi lldriver(i_clk_100mhz,
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spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
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spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
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spi_out, spi_valid, spi_busy,
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spi_out, spi_valid, spi_busy,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat,
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i_qspi_dat,
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i_qspi_dat);
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spi_dbg);
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// Erase status tracking
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// Erase status tracking
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reg write_in_progress, write_protect;
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reg write_in_progress, write_protect;
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reg [5:0] erased_sector;
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reg [5:0] erased_sector;
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reg dirty_sector;
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reg dirty_sector;
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reg [5:0] spif_return;
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reg [5:0] spif_return;
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reg spif_ctrl, spif_req;
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reg spif_ctrl, spif_req;
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wire [5:0] spif_sector;
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wire [5:0] spif_sector;
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assign spif_sector = spif_addr[19:14];
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assign spif_sector = spif_addr[19:14];
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assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
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initial state = `WBQSPI_RESET;
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initial state = `WBQSPI_RESET;
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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initial o_wb_stall = 1'b1;
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initial o_wb_stall = 1'b1;
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initial spi_wr = 1'b0;
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initial spi_wr = 1'b0;
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initial spi_len = 2'b00;
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initial spi_len = 2'b00;
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