| Line 49... |
Line 49... |
// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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`include "flash_config.v"
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//
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`define WBQSPI_RESET 0
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`define WBQSPI_RESET 0
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`define WBQSPI_RESET_QUADMODE 1
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`define WBQSPI_RESET_QUADMODE 1
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`define WBQSPI_IDLE 2
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`define WBQSPI_IDLE 2
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`define WBQSPI_RDIDLE 3 // Idle, but in fast read mode
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`define WBQSPI_RDIDLE 3 // Idle, but in fast read mode
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`define WBQSPI_WBDECODE 4
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`define WBQSPI_WBDECODE 4
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`define WBQSPI_WAIT_WIP_CLEAR 5
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`define WBQSPI_RD_DUMMY 5
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`define WBQSPI_CHECK_WIP_CLEAR 6
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`define WBQSPI_QRD_ADDRESS 6
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`define WBQSPI_CHECK_WIP_DONE 7
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`define WBQSPI_QRD_DUMMY 7
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`define WBQSPI_WEN 8
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`define WBQSPI_READ_CMD 8
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`define WBQSPI_PP 9 // Program page
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`define WBQSPI_READ_DATA 9
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`define WBQSPI_QPP 10 // Program page, 4 bit mode
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`define WBQSPI_WAIT_TIL_RDIDLE 10
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`define WBQSPI_WR_DATA 11
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`define WBQSPI_READ_ID_CMD 11
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`define WBQSPI_WR_BUS_CYCLE 12
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`define WBQSPI_READ_ID 12
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`define WBQSPI_RD_DUMMY 13
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`define WBQSPI_READ_STATUS 13
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`define WBQSPI_QRD_ADDRESS 14
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`define WBQSPI_READ_CONFIG 14
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`define WBQSPI_QRD_DUMMY 15
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`define WBQSPI_WAIT_TIL_IDLE 15
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`define WBQSPI_READ_CMD 16
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//
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`define WBQSPI_READ_DATA 17
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//
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`define WBQSPI_WAIT_TIL_RDIDLE 18
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`ifndef READ_ONLY
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`define WBQSPI_READ_ID_CMD 19
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//
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`define WBQSPI_READ_ID 20
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`define WBQSPI_WAIT_WIP_CLEAR 16
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`define WBQSPI_READ_STATUS 21
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`define WBQSPI_CHECK_WIP_CLEAR 17
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`define WBQSPI_READ_CONFIG 22
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`define WBQSPI_CHECK_WIP_DONE 18
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`define WBQSPI_WRITE_STATUS 23
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`define WBQSPI_WEN 19
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`define WBQSPI_WRITE_CONFIG 24
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`define WBQSPI_PP 20 // Program page
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`define WBQSPI_ERASE_WEN 25
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`define WBQSPI_QPP 21 // Program page, 4 bit mode
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`define WBQSPI_ERASE_CMD 26
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`define WBQSPI_WR_DATA 22
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`define WBQSPI_ERASE_BLOCK 27
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`define WBQSPI_WR_BUS_CYCLE 23
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`define WBQSPI_CLEAR_STATUS 28
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`define WBQSPI_WRITE_STATUS 24
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`define WBQSPI_IDLE_CHECK_WIP 29
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`define WBQSPI_WRITE_CONFIG 25
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`define WBQSPI_WAIT_TIL_IDLE 30
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`define WBQSPI_ERASE_WEN 26
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`define WBQSPI_ERASE_CMD 27
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`define WBQSPI_ERASE_BLOCK 28
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`define WBQSPI_CLEAR_STATUS 29
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`define WBQSPI_IDLE_CHECK_WIP 30
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//
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`endif
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module wbqspiflash(i_clk_100mhz,
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module wbqspiflash(i_clk_100mhz,
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// Internal wishbone connections
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// Internal wishbone connections
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i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
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i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
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i_wb_addr, i_wb_data,
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i_wb_addr, i_wb_data,
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// Wishbone return values
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// Wishbone return values
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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// Quad Spi connections to the external device
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// Quad Spi connections to the external device
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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o_interrupt);
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o_interrupt);
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parameter ADDRESS_WIDTH=22;
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input i_clk_100mhz;
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input i_clk_100mhz;
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// Wishbone, inputs first
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// Wishbone, inputs first
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input [19:0] i_wb_addr;
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input [(ADDRESS_WIDTH-3):0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// then outputs
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// then outputs
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output reg o_wb_ack;
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output reg o_wb_ack;
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output reg o_wb_stall;
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output reg o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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| Line 106... |
Line 116... |
output wire [1:0] o_qspi_mod;
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output wire [1:0] o_qspi_mod;
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output wire [3:0] o_qspi_dat;
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output wire [3:0] o_qspi_dat;
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input [3:0] i_qspi_dat;
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input [3:0] i_qspi_dat;
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// Interrupt line
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// Interrupt line
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output reg o_interrupt;
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output reg o_interrupt;
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// output wire [31:0] o_debug;
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|
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reg spi_wr, spi_hold, spi_spd, spi_dir;
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reg spi_wr, spi_hold, spi_spd, spi_dir;
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reg [31:0] spi_in;
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reg [31:0] spi_in;
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reg [1:0] spi_len;
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reg [1:0] spi_len;
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wire [31:0] spi_out;
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wire [31:0] spi_out;
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wire spi_valid, spi_busy;
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wire spi_valid, spi_busy;
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wire w_qspi_sck, w_qspi_cs_n;
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wire w_qspi_sck, w_qspi_cs_n;
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wire [3:0] w_qspi_dat;
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wire [3:0] w_qspi_dat;
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wire [1:0] w_qspi_mod;
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wire [1:0] w_qspi_mod;
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// wire [22:0] spi_dbg;
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llqspi lldriver(i_clk_100mhz,
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llqspi lldriver(i_clk_100mhz,
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spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
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spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
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spi_out, spi_valid, spi_busy,
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spi_out, spi_valid, spi_busy,
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w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
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w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
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i_qspi_dat);
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i_qspi_dat);
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|
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// Erase status tracking
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// Erase status tracking
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reg write_in_progress, write_protect;
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reg write_in_progress, write_protect;
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reg [5:0] erased_sector;
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reg [(ADDRESS_WIDTH-17):0] erased_sector;
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reg dirty_sector;
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reg dirty_sector;
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initial begin
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initial begin
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write_in_progress = 1'b0;
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write_in_progress = 1'b0;
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erased_sector = 6'h00;
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erased_sector = 0;
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dirty_sector = 1'b1;
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dirty_sector = 1'b1;
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write_protect = 1'b1;
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write_protect = 1'b1;
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end
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end
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reg [7:0] last_status;
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reg [7:0] last_status;
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reg quad_mode_enabled;
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reg quad_mode_enabled;
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reg spif_cmd, spif_override;
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reg spif_cmd, spif_override;
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reg [19:0] spif_addr;
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reg [(ADDRESS_WIDTH-3):0] spif_addr;
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reg [31:0] spif_data;
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reg [31:0] spif_data;
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reg [5:0] state;
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reg [5:0] state;
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reg spif_ctrl, spif_req;
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reg spif_ctrl, spif_req;
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wire [5:0] spif_sector;
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wire [(ADDRESS_WIDTH-17):0] spif_sector;
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assign spif_sector = spif_addr[19:14];
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assign spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];
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// assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
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|
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initial state = `WBQSPI_RESET;
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initial state = `WBQSPI_RESET;
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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initial o_wb_stall = 1'b1;
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initial o_wb_stall = 1'b1;
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initial spi_wr = 1'b0;
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initial spi_wr = 1'b0;
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| Line 213... |
Line 227... |
if ((i_wb_data_stb)&&(i_wb_cyc))
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if ((i_wb_data_stb)&&(i_wb_cyc))
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begin
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begin
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|
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if (i_wb_we) // Request to write a page
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if (i_wb_we) // Request to write a page
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begin
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begin
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`ifdef READ_ONLY
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o_wb_ack <= 1'b1;
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o_wb_stall <= 1'b0;
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end else
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`else
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if((~write_protect)&&(~write_in_progress))
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if((~write_protect)&&(~write_in_progress))
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begin // 00
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begin // 00
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spi_wr <= 1'b1;
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spi_wr <= 1'b1;
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spi_len <= 2'b00; // 8 bits
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spi_len <= 2'b00; // 8 bits
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// Send a write enable command
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// Send a write enable command
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| Line 237... |
Line 256... |
state <= `WBQSPI_WAIT_WIP_CLEAR;
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state <= `WBQSPI_WAIT_WIP_CLEAR;
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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end
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end
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end else if (~write_in_progress)
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end else if (~write_in_progress)
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`endif
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begin // Read access, normal mode(s)
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begin // Read access, normal mode(s)
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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spi_wr <= 1'b1; // Write cmd to device
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spi_wr <= 1'b1; // Write cmd to device
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if (quad_mode_enabled)
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if (quad_mode_enabled)
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begin
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begin
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spi_in <= { 8'heb, 2'b00, i_wb_addr[19:0], 2'b00 };
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spi_in <= { 8'heb,
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{(24-ADDRESS_WIDTH){1'b0}},
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i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
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state <= `WBQSPI_QRD_ADDRESS;
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state <= `WBQSPI_QRD_ADDRESS;
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spi_len <= 2'b00; // single byte, cmd only
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spi_len <= 2'b00; // single byte, cmd only
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end else begin
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end else begin
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spi_in <= { 8'h0b, 2'b00, i_wb_addr[19:0], 2'b00 };
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spi_in <= { 8'h0b,
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{(24-ADDRESS_WIDTH){1'b0}},
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i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
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state <= `WBQSPI_RD_DUMMY;
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state <= `WBQSPI_RD_DUMMY;
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spi_len <= 2'b11; // cmd+addr,32bits
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spi_len <= 2'b11; // cmd+addr,32bits
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end
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end
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`ifndef READ_ONLY
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end else begin
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end else begin
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// A write is in progress ... need to stall
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// A write is in progress ... need to stall
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// the bus until the write is complete.
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// the bus until the write is complete.
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state <= `WBQSPI_WAIT_WIP_CLEAR;
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state <= `WBQSPI_WAIT_WIP_CLEAR;
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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`endif
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end
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end
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end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
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end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
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begin
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begin
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`ifdef READ_ONLY
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o_wb_ack <= 1'b1;
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o_wb_stall <= 1'b0;
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`else
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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case(i_wb_addr[1:0])
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case(i_wb_addr[1:0])
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2'b00: begin // Erase command register
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2'b00: begin // Erase command register
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write_protect <= ~i_wb_data[28];
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write_protect <= ~i_wb_data[28];
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o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
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| Line 319... |
Line 349... |
2'b11: begin // Write the ID register??? makes no sense
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2'b11: begin // Write the ID register??? makes no sense
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o_wb_ack <= 1'b1;
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o_wb_ack <= 1'b1;
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o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
|
end
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end
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endcase
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endcase
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|
`endif
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end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
|
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
|
begin
|
begin
|
case(i_wb_addr[1:0])
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case(i_wb_addr[1:0])
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2'b00: begin // Read local register
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2'b00: begin // Read local register
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if (write_in_progress) // Read status
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if (write_in_progress) // Read status
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| Line 339... |
Line 370... |
o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
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o_wb_data <= { write_in_progress,
|
o_wb_data <= { write_in_progress,
|
dirty_sector, spi_busy,
|
dirty_sector, spi_busy,
|
~write_protect,
|
~write_protect,
|
quad_mode_enabled,
|
quad_mode_enabled,
|
7'h00,
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{(29-ADDRESS_WIDTH){1'b0}},
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erased_sector, 14'h000 };
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erased_sector, 14'h000 };
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end end
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end end
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2'b01: begin // Read configuration register
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2'b01: begin // Read configuration register
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state <= `WBQSPI_READ_CONFIG;
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state <= `WBQSPI_READ_CONFIG;
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spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
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| Line 370... |
Line 401... |
|
|
o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
endcase
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endcase
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`ifndef READ_ONLY
|
end else if ((~i_wb_cyc)&&(write_in_progress))
|
end else if ((~i_wb_cyc)&&(write_in_progress))
|
begin
|
begin
|
state <= `WBQSPI_IDLE_CHECK_WIP;
|
state <= `WBQSPI_IDLE_CHECK_WIP;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_in <= { 8'h05, 24'h00};
|
spi_in <= { 8'h05, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
|
|
`endif
|
end
|
end
|
end else if (state == `WBQSPI_RDIDLE)
|
end else if (state == `WBQSPI_RDIDLE)
|
begin
|
begin
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
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| Line 398... |
Line 431... |
if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we))
|
if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we))
|
begin // Continue our read ... send the new address / mode
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begin // Continue our read ... send the new address / mode
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b10; // Write address, but not mode byte
|
spi_len <= 2'b10; // Write address, but not mode byte
|
spi_in <= { 2'h0, i_wb_addr[19:0], 2'h0, 8'ha0 };
|
spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
|
|
i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
|
state <= `WBQSPI_QRD_DUMMY;
|
state <= `WBQSPI_QRD_DUMMY;
|
end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
|
end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
|
begin
|
begin
|
// A local read that doesn't touch the device, so leave
|
// A local read that doesn't touch the device, so leave
|
// the device in its current state
|
// the device in its current state
|
| Line 410... |
Line 444... |
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_data <= { write_in_progress,
|
o_wb_data <= { write_in_progress,
|
dirty_sector, spi_busy,
|
dirty_sector, spi_busy,
|
~write_protect,
|
~write_protect,
|
quad_mode_enabled,
|
quad_mode_enabled,
|
7'h00,
|
{(29-ADDRESS_WIDTH){1'b0}},
|
erased_sector, 14'h000 };
|
erased_sector, 14'h000 };
|
end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb)))
|
end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb)))
|
begin // Need to release the device from quad mode for all else
|
begin // Need to release the device from quad mode for all else
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
| Line 443... |
Line 477... |
// Data register access
|
// Data register access
|
if (~spif_ctrl)
|
if (~spif_ctrl)
|
begin
|
begin
|
if (spif_cmd) // Request to write a page
|
if (spif_cmd) // Request to write a page
|
begin
|
begin
|
|
`ifdef READ_ONLY
|
|
o_wb_ack <= spif_req;
|
|
o_wb_stall <= 1'b0;
|
|
state <= `WBQSPI_IDLE;
|
|
`else
|
if((~write_protect)&&(~write_in_progress))
|
if((~write_protect)&&(~write_in_progress))
|
begin // 00
|
begin // 00
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00; // 8 bits
|
spi_len <= 2'b00; // 8 bits
|
// Send a write enable command
|
// Send a write enable command
|
| Line 469... |
Line 508... |
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
// end else if (~write_in_progress) // always true
|
// end else if (~write_in_progress) // always true
|
// but ... we wouldn't get here on a normal read access
|
// but ... we wouldn't get here on a normal read access
|
|
`endif
|
end else begin
|
end else begin
|
// Something's wrong, we should never get here
|
// Something's wrong, we should never
|
|
// get here
|
// Attempt to go to idle to recover
|
// Attempt to go to idle to recover
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
end
|
end
|
end else if ((spif_ctrl)&&(spif_cmd))
|
end else if ((spif_ctrl)&&(spif_cmd))
|
begin
|
begin
|
|
`ifdef READ_ONLY
|
|
o_wb_ack <= spif_req;
|
|
o_wb_stall <= 1'b0;
|
|
state <= `WBQSPI_IDLE;
|
|
`else
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
case(spif_addr[1:0])
|
case(spif_addr[1:0])
|
2'b00: begin // Erase command register
|
2'b00: begin // Erase command register
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
| Line 527... |
Line 573... |
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
end
|
end
|
endcase
|
endcase
|
|
`endif
|
end else begin // on (~spif_we)
|
end else begin // on (~spif_we)
|
case(spif_addr[1:0])
|
case(spif_addr[1:0])
|
2'b00: begin // Read local register
|
2'b00: begin // Read local register
|
// Nonsense case--would've done this
|
// Nonsense case--would've done this
|
// already
|
// already
|
| Line 566... |
Line 613... |
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
|
//
|
begin
|
//
|
o_wb_stall <= 1'b1;
|
// READ DATA section: for both data and commands
|
o_wb_ack <= 1'b0;
|
//
|
spi_wr <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if (~spi_busy)
|
|
begin
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h05, 24'h0000 };
|
|
spi_hold <= 1'b1;
|
|
spi_len <= 2'b01; // 16 bits write, so we can read 8
|
|
state <= `WBQSPI_CHECK_WIP_CLEAR;
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
end
|
|
end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
// Repeat as often as necessary until we are clear
|
|
spi_wr <= 1'b1;
|
|
spi_in <= 32'h0000; // Values here are actually irrelevant
|
|
spi_hold <= 1'b1;
|
|
spi_len <= 2'b00; // One byte at a time
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((spi_valid)&&(~spi_out[0]))
|
|
begin
|
|
state <= `WBQSPI_CHECK_WIP_DONE;
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b0;
|
|
write_in_progress <= 1'b0;
|
|
last_status <= spi_out[7:0];
|
|
end
|
|
end else if (state == `WBQSPI_CHECK_WIP_DONE)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
// Let's let the SPI port come back to a full idle,
|
|
// and the chip select line go low before continuing
|
|
spi_wr <= 1'b0;
|
|
spi_len <= 2'b00;
|
|
spi_hold <= 1'b0;
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
|
|
begin
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b0;
|
|
|
|
casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
|
|
4'b00??: begin // Read data from ... somewhere
|
|
spi_wr <= 1'b1; // Write cmd to device
|
|
if (quad_mode_enabled)
|
|
begin
|
|
spi_in <= { 8'heb, 2'b00, spif_addr[19:0], 2'b00 };
|
|
state <= `WBQSPI_QRD_ADDRESS;
|
|
// spi_len <= 2'b00; // single byte, cmd only
|
|
end else begin
|
|
spi_in <= { 8'h0b, 2'b00, spif_addr[19:0], 2'b00 };
|
|
state <= `WBQSPI_RD_DUMMY;
|
|
spi_len <= 2'b11; // Send cmd and addr
|
|
end end
|
|
4'b10??: begin // Write data to ... anywhere
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b00; // 8 bits
|
|
// Send a write enable command
|
|
spi_in <= { 8'h06, 24'h00 };
|
|
state <= `WBQSPI_WEN;
|
|
end
|
|
4'b0110: begin // Read status register
|
|
state <= `WBQSPI_READ_STATUS;
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
|
spi_in <= { 8'h05, 24'h00};
|
|
end
|
|
4'b0111: begin
|
|
state <= `WBQSPI_READ_ID_CMD;
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b00;
|
|
spi_in <= { 8'h9f, 24'h00};
|
|
end
|
|
default: begin //
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= spif_req;
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
end
|
|
endcase
|
|
// spif_cmd <= i_wb_we;
|
|
// spif_addr <= i_wb_addr;
|
|
// spif_data <= i_wb_data;
|
|
// spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
|
|
// spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
|
|
end
|
|
end else if (state == `WBQSPI_WEN)
|
|
begin // We came here after issuing a write enable command
|
|
spi_wr <= 1'b0;
|
|
o_wb_ack <= 1'b0;
|
|
o_wb_stall <= 1'b1;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
|
|
state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
|
|
// state <= `WBQSPI_PP;
|
|
end else if (state == `WBQSPI_PP)
|
|
begin // We come here under a full stop / full port idle mode
|
|
// Issue our command immediately
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h02, 2'h0, spif_addr, 2'b00 };
|
|
spi_len <= 2'b11;
|
|
spi_hold <= 1'b1;
|
|
spi_spd <= 1'b0;
|
|
spi_dir <= 1'b0; // Writing
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
|
// Once we get busy, move on
|
|
if (spi_busy)
|
|
state <= `WBQSPI_WR_DATA;
|
|
if (spif_sector == erased_sector)
|
|
dirty_sector <= 1'b1;
|
|
end else if (state == `WBQSPI_QPP)
|
|
begin // We come here under a full stop / full port idle mode
|
|
// Issue our command immediately
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h32, 2'h0, spif_addr, 2'b00 };
|
|
spi_len <= 2'b11;
|
|
spi_hold <= 1'b1;
|
|
spi_spd <= 1'b0;
|
|
spi_dir <= 1'b0; // Writing
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
|
// Once we get busy, move on
|
|
if (spi_busy)
|
|
begin
|
|
// spi_wr is irrelevant here ...
|
|
// Set the speed value once, but wait til we get busy
|
|
// to do so.
|
|
spi_spd <= 1'b1;
|
|
state <= `WBQSPI_WR_DATA;
|
|
end
|
|
if (spif_sector == erased_sector)
|
|
dirty_sector <= 1'b1;
|
|
end else if (state == `WBQSPI_WR_DATA)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
spi_wr <= 1'b1; // write without waiting
|
|
spi_in <= {
|
|
spif_data[ 7: 0],
|
|
spif_data[15: 8],
|
|
spif_data[23:16],
|
|
spif_data[31:24] };
|
|
spi_len <= 2'b11; // Write 4 bytes
|
|
spi_hold <= 1'b1;
|
|
if (~spi_busy)
|
|
begin
|
|
o_wb_ack <= spif_req; // Ack when command given
|
|
state <= `WBQSPI_WR_BUS_CYCLE;
|
|
end
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
end else if (state == `WBQSPI_WR_BUS_CYCLE)
|
|
begin
|
|
o_wb_ack <= 1'b0; // Turn off our ack and stall flags
|
|
o_wb_stall <= 1'b1;
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b1;
|
|
write_in_progress <= 1'b1;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if (~i_wb_cyc)
|
|
begin
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
spi_hold <= 1'b0;
|
|
end else if (spi_wr)
|
|
begin // Give the SPI a chance to get busy on the last write
|
|
// Do nothing here.
|
|
end else if ((i_wb_data_stb)&&(i_wb_we)
|
|
&&(i_wb_addr == (spif_addr+1))
|
|
&&(i_wb_addr[19:6]==spif_addr[19:6]))
|
|
begin
|
|
spif_cmd <= 1'b1;
|
|
spif_data <= i_wb_data;
|
|
spif_addr <= i_wb_addr;
|
|
spif_ctrl <= 1'b0;
|
|
spif_req<= 1'b1;
|
|
// We'll keep the bus stalled on this request
|
|
// for a while
|
|
state <= `WBQSPI_WR_DATA;
|
|
o_wb_ack <= 1'b0;
|
|
o_wb_stall <= 1'b0;
|
|
end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
|
|
begin
|
|
spi_hold <= 1'b0;
|
|
spi_wr <= 1'b0;
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
end // Otherwise we stay here
|
|
end else if (state == `WBQSPI_RD_DUMMY)
|
end else if (state == `WBQSPI_RD_DUMMY)
|
begin
|
begin
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
| Line 789... |
Line 643... |
// address (24-bits) and mode (8-bits) in quad speed.
|
// address (24-bits) and mode (8-bits) in quad speed.
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_wr <= 1'b1; // Non-stop
|
spi_wr <= 1'b1; // Non-stop
|
spi_in <= { 2'b0, spif_addr, 2'b0, 8'ha0 };
|
spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
|
|
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
|
spi_len <= 2'b10; // Write address, not mode byte
|
spi_len <= 2'b10; // Write address, not mode byte
|
spi_spd <= 1'b1;
|
spi_spd <= 1'b1;
|
spi_dir <= 1'b0; // Still writing
|
spi_dir <= 1'b0; // Still writing
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
| Line 948... |
Line 803... |
begin // status, 'cause we're writing
|
begin // status, 'cause we're writing
|
o_wb_data <= { spi_out[0],
|
o_wb_data <= { spi_out[0],
|
dirty_sector, spi_busy,
|
dirty_sector, spi_busy,
|
~write_protect,
|
~write_protect,
|
quad_mode_enabled,
|
quad_mode_enabled,
|
7'h00,
|
{(29-ADDRESS_WIDTH){1'b0}},
|
erased_sector, 14'h000 };
|
erased_sector, 14'h000 };
|
end else begin
|
end else begin
|
o_wb_data <= { 24'h00, spi_out[7:0] };
|
o_wb_data <= { 24'h00, spi_out[7:0] };
|
end
|
end
|
end
|
end
|
| Line 979... |
Line 834... |
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
spif_req <= 1'b0;
|
spif_req <= 1'b0;
|
end
|
end
|
|
|
|
//
|
|
//
|
|
// Write/erase data section
|
|
//
|
|
`ifndef READ_ONLY
|
|
end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
spi_wr <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if (~spi_busy)
|
|
begin
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h05, 24'h0000 };
|
|
spi_hold <= 1'b1;
|
|
spi_len <= 2'b01; // 16 bits write, so we can read 8
|
|
state <= `WBQSPI_CHECK_WIP_CLEAR;
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
end
|
|
end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
// Repeat as often as necessary until we are clear
|
|
spi_wr <= 1'b1;
|
|
spi_in <= 32'h0000; // Values here are actually irrelevant
|
|
spi_hold <= 1'b1;
|
|
spi_len <= 2'b00; // One byte at a time
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((spi_valid)&&(~spi_out[0]))
|
|
begin
|
|
state <= `WBQSPI_CHECK_WIP_DONE;
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b0;
|
|
write_in_progress <= 1'b0;
|
|
last_status <= spi_out[7:0];
|
|
end
|
|
end else if (state == `WBQSPI_CHECK_WIP_DONE)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
// Let's let the SPI port come back to a full idle,
|
|
// and the chip select line go low before continuing
|
|
spi_wr <= 1'b0;
|
|
spi_len <= 2'b00;
|
|
spi_hold <= 1'b0;
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
|
|
begin
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b0;
|
|
|
|
casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
|
|
4'b00??: begin // Read data from ... somewhere
|
|
spi_wr <= 1'b1; // Write cmd to device
|
|
if (quad_mode_enabled)
|
|
begin
|
|
spi_in <= { 8'heb,
|
|
{(24-ADDRESS_WIDTH){1'b0}},
|
|
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
|
|
state <= `WBQSPI_QRD_ADDRESS;
|
|
// spi_len <= 2'b00; // single byte, cmd only
|
|
end else begin
|
|
spi_in <= { 8'h0b,
|
|
{(24-ADDRESS_WIDTH){1'b0}},
|
|
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
|
|
state <= `WBQSPI_RD_DUMMY;
|
|
spi_len <= 2'b11; // Send cmd and addr
|
|
end end
|
|
4'b10??: begin // Write data to ... anywhere
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b00; // 8 bits
|
|
// Send a write enable command
|
|
spi_in <= { 8'h06, 24'h00 };
|
|
state <= `WBQSPI_WEN;
|
|
end
|
|
4'b0110: begin // Read status register
|
|
state <= `WBQSPI_READ_STATUS;
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
|
spi_in <= { 8'h05, 24'h00};
|
|
end
|
|
4'b0111: begin
|
|
state <= `WBQSPI_READ_ID_CMD;
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b00;
|
|
spi_in <= { 8'h9f, 24'h00};
|
|
end
|
|
default: begin //
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= spif_req;
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
end
|
|
endcase
|
|
// spif_cmd <= i_wb_we;
|
|
// spif_addr <= i_wb_addr;
|
|
// spif_data <= i_wb_data;
|
|
// spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
|
|
// spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
|
|
end
|
|
end else if (state == `WBQSPI_WEN)
|
|
begin // We came here after issuing a write enable command
|
|
spi_wr <= 1'b0;
|
|
o_wb_ack <= 1'b0;
|
|
o_wb_stall <= 1'b1;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
|
|
state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
|
|
// state <= `WBQSPI_PP;
|
|
end else if (state == `WBQSPI_PP)
|
|
begin // We come here under a full stop / full port idle mode
|
|
// Issue our command immediately
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h02,
|
|
{(24-ADDRESS_WIDTH){1'b0}},
|
|
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
|
|
spi_len <= 2'b11;
|
|
spi_hold <= 1'b1;
|
|
spi_spd <= 1'b0;
|
|
spi_dir <= 1'b0; // Writing
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
|
// Once we get busy, move on
|
|
if (spi_busy)
|
|
state <= `WBQSPI_WR_DATA;
|
|
if (spif_sector == erased_sector)
|
|
dirty_sector <= 1'b1;
|
|
end else if (state == `WBQSPI_QPP)
|
|
begin // We come here under a full stop / full port idle mode
|
|
// Issue our command immediately
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h32,
|
|
{(24-ADDRESS_WIDTH){1'b0}},
|
|
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
|
|
spi_len <= 2'b11;
|
|
spi_hold <= 1'b1;
|
|
spi_spd <= 1'b0;
|
|
spi_dir <= 1'b0; // Writing
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
|
// Once we get busy, move on
|
|
if (spi_busy)
|
|
begin
|
|
// spi_wr is irrelevant here ...
|
|
// Set the speed value once, but wait til we get busy
|
|
// to do so.
|
|
spi_spd <= 1'b1;
|
|
state <= `WBQSPI_WR_DATA;
|
|
end
|
|
if (spif_sector == erased_sector)
|
|
dirty_sector <= 1'b1;
|
|
end else if (state == `WBQSPI_WR_DATA)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
spi_wr <= 1'b1; // write without waiting
|
|
spi_in <= {
|
|
spif_data[ 7: 0],
|
|
spif_data[15: 8],
|
|
spif_data[23:16],
|
|
spif_data[31:24] };
|
|
spi_len <= 2'b11; // Write 4 bytes
|
|
spi_hold <= 1'b1;
|
|
if (~spi_busy)
|
|
begin
|
|
o_wb_ack <= spif_req; // Ack when command given
|
|
state <= `WBQSPI_WR_BUS_CYCLE;
|
|
end
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
end else if (state == `WBQSPI_WR_BUS_CYCLE)
|
|
begin
|
|
o_wb_ack <= 1'b0; // Turn off our ack and stall flags
|
|
o_wb_stall <= 1'b1;
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b1;
|
|
write_in_progress <= 1'b1;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if (~i_wb_cyc)
|
|
begin
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
spi_hold <= 1'b0;
|
|
end else if (spi_wr)
|
|
begin // Give the SPI a chance to get busy on the last write
|
|
// Do nothing here.
|
|
end else if ((i_wb_data_stb)&&(i_wb_we)
|
|
&&(i_wb_addr == (spif_addr+1))
|
|
&&(i_wb_addr[(ADDRESS_WIDTH-3):6]==spif_addr[(ADDRESS_WIDTH-3):6]))
|
|
begin
|
|
spif_cmd <= 1'b1;
|
|
spif_data <= i_wb_data;
|
|
spif_addr <= i_wb_addr;
|
|
spif_ctrl <= 1'b0;
|
|
spif_req<= 1'b1;
|
|
// We'll keep the bus stalled on this request
|
|
// for a while
|
|
state <= `WBQSPI_WR_DATA;
|
|
o_wb_ack <= 1'b0;
|
|
o_wb_stall <= 1'b0;
|
|
end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
|
|
begin
|
|
spi_hold <= 1'b0;
|
|
spi_wr <= 1'b0;
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
end // Otherwise we stay here
|
end else if (state == `WBQSPI_WRITE_CONFIG)
|
end else if (state == `WBQSPI_WRITE_CONFIG)
|
begin // We enter immediately after commanding a WEN
|
begin // We enter immediately after commanding a WEN
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
| Line 1034... |
Line 1100... |
spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
|
spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
|
spi_len <= 2'b11; // 32 bit write
|
spi_len <= 2'b11; // 32 bit write
|
// together with setting our copy of the WIP bit
|
// together with setting our copy of the WIP bit
|
write_in_progress <= 1'b1;
|
write_in_progress <= 1'b1;
|
// keeping track of which sector we just erased
|
// keeping track of which sector we just erased
|
erased_sector <= spif_data[19:14];
|
erased_sector <= spif_data[(ADDRESS_WIDTH-3):14];
|
// and marking this erase sector as no longer dirty
|
// and marking this erase sector as no longer dirty
|
dirty_sector <= 1'b0;
|
dirty_sector <= 1'b0;
|
|
|
// Wait for a full stop before issuing this command
|
// Wait for a full stop before issuing this command
|
if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
|
if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
|
| Line 1098... |
Line 1164... |
begin // We can now go to idle and process a command
|
begin // We can now go to idle and process a command
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
end
|
end
|
|
`endif // !READ_ONLY
|
end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
|
end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
|
begin
|
begin
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
