///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbspiflash.v
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// Filename: wbspiflash.v
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//
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//
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// Project: Wishbone Controlled Quad SPI Flash Controller
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// Project: Wishbone Controlled Quad SPI Flash Controller
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//
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//
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// Purpose: Access a Quad SPI flash via a WISHBONE interface. This
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// Purpose: Access a Quad SPI flash via a WISHBONE interface. This
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// includes both read and write (and erase) commands to the SPI
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// includes both read and write (and erase) commands to the SPI
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// flash. All read/write commands are accomplished using the
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// flash. All read/write commands are accomplished using the
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// high speed (4-bit) interface. Further, the device will be
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// high speed (4-bit) interface. Further, the device will be
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// left/kept in the 4-bit read interface mode between accesses,
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// left/kept in the 4-bit read interface mode between accesses,
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// for a minimum read latency.
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// for a minimum read latency.
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//
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//
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// Wishbone Registers (See spec sheet for more detail):
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// Wishbone Registers (See spec sheet for more detail):
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// 0: local config(r) / erase commands(w) / deep power down cmds / etc.
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// 0: local config(r) / erase commands(w) / deep power down cmds / etc.
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// R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
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// R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
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// { last_erased_sector, 14'h00 } if (WIP)
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// { last_erased_sector, 14'h00 } if (WIP)
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// else { current_sector_being_erased, 14'h00 }
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// else { current_sector_being_erased, 14'h00 }
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// current if write in progress, last if written
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// current if write in progress, last if written
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// W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
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// W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
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// 1: Configuration register
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// 1: Configuration register
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// 2: Status register (R/w)
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// 2: Status register (R/w)
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// 3: Read ID (read only)
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// 3: Read ID (read only)
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// (19 bits): Data (R/w, but expect writes to take a while)
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// (19 bits): Data (R/w, but expect writes to take a while)
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//
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//
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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`include "flash_config.v"
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//
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`define WBQSPI_RESET 0
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`define WBQSPI_RESET 0
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`define WBQSPI_RESET_QUADMODE 1
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`define WBQSPI_RESET_QUADMODE 1
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`define WBQSPI_IDLE 2
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`define WBQSPI_IDLE 2
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`define WBQSPI_RDIDLE 3 // Idle, but in fast read mode
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`define WBQSPI_RDIDLE 3 // Idle, but in fast read mode
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`define WBQSPI_WBDECODE 4
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`define WBQSPI_WBDECODE 4
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`define WBQSPI_WAIT_WIP_CLEAR 5
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`define WBQSPI_RD_DUMMY 5
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`define WBQSPI_CHECK_WIP_CLEAR 6
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`define WBQSPI_QRD_ADDRESS 6
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`define WBQSPI_CHECK_WIP_DONE 7
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`define WBQSPI_QRD_DUMMY 7
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`define WBQSPI_WEN 8
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`define WBQSPI_READ_CMD 8
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`define WBQSPI_PP 9 // Program page
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`define WBQSPI_READ_DATA 9
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`define WBQSPI_QPP 10 // Program page, 4 bit mode
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`define WBQSPI_WAIT_TIL_RDIDLE 10
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`define WBQSPI_WR_DATA 11
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`define WBQSPI_READ_ID_CMD 11
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`define WBQSPI_WR_BUS_CYCLE 12
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`define WBQSPI_READ_ID 12
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`define WBQSPI_RD_DUMMY 13
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`define WBQSPI_READ_STATUS 13
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`define WBQSPI_QRD_ADDRESS 14
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`define WBQSPI_READ_CONFIG 14
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`define WBQSPI_QRD_DUMMY 15
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`define WBQSPI_WAIT_TIL_IDLE 15
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`define WBQSPI_READ_CMD 16
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//
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`define WBQSPI_READ_DATA 17
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//
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`define WBQSPI_WAIT_TIL_RDIDLE 18
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`ifndef READ_ONLY
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`define WBQSPI_READ_ID_CMD 19
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//
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`define WBQSPI_READ_ID 20
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`define WBQSPI_WAIT_WIP_CLEAR 16
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`define WBQSPI_READ_STATUS 21
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`define WBQSPI_CHECK_WIP_CLEAR 17
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`define WBQSPI_READ_CONFIG 22
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`define WBQSPI_CHECK_WIP_DONE 18
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`define WBQSPI_WRITE_STATUS 23
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`define WBQSPI_WEN 19
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`define WBQSPI_WRITE_CONFIG 24
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`define WBQSPI_PP 20 // Program page
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`define WBQSPI_ERASE_WEN 25
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`define WBQSPI_QPP 21 // Program page, 4 bit mode
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`define WBQSPI_ERASE_CMD 26
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`define WBQSPI_WR_DATA 22
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`define WBQSPI_ERASE_BLOCK 27
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`define WBQSPI_WR_BUS_CYCLE 23
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`define WBQSPI_CLEAR_STATUS 28
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`define WBQSPI_WRITE_STATUS 24
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`define WBQSPI_IDLE_CHECK_WIP 29
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`define WBQSPI_WRITE_CONFIG 25
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`define WBQSPI_WAIT_TIL_IDLE 30
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`define WBQSPI_ERASE_WEN 26
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`define WBQSPI_ERASE_CMD 27
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`define WBQSPI_ERASE_BLOCK 28
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`define WBQSPI_CLEAR_STATUS 29
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`define WBQSPI_IDLE_CHECK_WIP 30
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//
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`endif
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module wbqspiflash(i_clk_100mhz,
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module wbqspiflash(i_clk_100mhz,
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// Internal wishbone connections
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// Internal wishbone connections
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i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
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i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
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i_wb_addr, i_wb_data,
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i_wb_addr, i_wb_data,
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// Wishbone return values
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// Wishbone return values
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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// Quad Spi connections to the external device
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// Quad Spi connections to the external device
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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o_interrupt);
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o_interrupt);
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parameter ADDRESS_WIDTH=22;
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input i_clk_100mhz;
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input i_clk_100mhz;
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// Wishbone, inputs first
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// Wishbone, inputs first
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input [19:0] i_wb_addr;
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input [(ADDRESS_WIDTH-3):0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// then outputs
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// then outputs
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output reg o_wb_ack;
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output reg o_wb_ack;
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output reg o_wb_stall;
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output reg o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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// Quad SPI control wires
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// Quad SPI control wires
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output wire o_qspi_sck, o_qspi_cs_n;
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output wire o_qspi_sck, o_qspi_cs_n;
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output wire [1:0] o_qspi_mod;
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output wire [1:0] o_qspi_mod;
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output wire [3:0] o_qspi_dat;
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output wire [3:0] o_qspi_dat;
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input [3:0] i_qspi_dat;
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input [3:0] i_qspi_dat;
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// Interrupt line
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// Interrupt line
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output reg o_interrupt;
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output reg o_interrupt;
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// output wire [31:0] o_debug;
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reg spi_wr, spi_hold, spi_spd, spi_dir;
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reg spi_wr, spi_hold, spi_spd, spi_dir;
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reg [31:0] spi_in;
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reg [31:0] spi_in;
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reg [1:0] spi_len;
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reg [1:0] spi_len;
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wire [31:0] spi_out;
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wire [31:0] spi_out;
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wire spi_valid, spi_busy;
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wire spi_valid, spi_busy;
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wire w_qspi_sck, w_qspi_cs_n;
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wire w_qspi_sck, w_qspi_cs_n;
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wire [3:0] w_qspi_dat;
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wire [3:0] w_qspi_dat;
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wire [1:0] w_qspi_mod;
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wire [1:0] w_qspi_mod;
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// wire [22:0] spi_dbg;
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llqspi lldriver(i_clk_100mhz,
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llqspi lldriver(i_clk_100mhz,
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spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
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spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
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spi_out, spi_valid, spi_busy,
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spi_out, spi_valid, spi_busy,
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w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
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w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
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i_qspi_dat);
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i_qspi_dat);
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// Erase status tracking
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// Erase status tracking
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reg write_in_progress, write_protect;
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reg write_in_progress, write_protect;
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reg [5:0] erased_sector;
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reg [(ADDRESS_WIDTH-17):0] erased_sector;
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reg dirty_sector;
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reg dirty_sector;
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initial begin
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initial begin
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write_in_progress = 1'b0;
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write_in_progress = 1'b0;
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erased_sector = 6'h00;
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erased_sector = 0;
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dirty_sector = 1'b1;
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dirty_sector = 1'b1;
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write_protect = 1'b1;
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write_protect = 1'b1;
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end
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end
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reg [7:0] last_status;
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reg [7:0] last_status;
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reg quad_mode_enabled;
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reg quad_mode_enabled;
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reg spif_cmd, spif_override;
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reg spif_cmd, spif_override;
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reg [19:0] spif_addr;
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reg [(ADDRESS_WIDTH-3):0] spif_addr;
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reg [31:0] spif_data;
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reg [31:0] spif_data;
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reg [5:0] state;
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reg [5:0] state;
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reg spif_ctrl, spif_req;
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reg spif_ctrl, spif_req;
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wire [5:0] spif_sector;
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wire [(ADDRESS_WIDTH-17):0] spif_sector;
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assign spif_sector = spif_addr[19:14];
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assign spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];
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// assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
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initial state = `WBQSPI_RESET;
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initial state = `WBQSPI_RESET;
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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initial o_wb_stall = 1'b1;
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initial o_wb_stall = 1'b1;
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initial spi_wr = 1'b0;
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initial spi_wr = 1'b0;
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initial spi_len = 2'b00;
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initial spi_len = 2'b00;
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initial quad_mode_enabled = 1'b0;
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initial quad_mode_enabled = 1'b0;
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initial o_interrupt = 1'b0;
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initial o_interrupt = 1'b0;
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always @(posedge i_clk_100mhz)
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always @(posedge i_clk_100mhz)
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begin
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begin
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spif_override <= 1'b0;
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spif_override <= 1'b0;
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if (state == `WBQSPI_RESET)
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if (state == `WBQSPI_RESET)
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begin
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begin
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// From a reset, we should
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// From a reset, we should
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// Enable the Quad I/O mode
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// Enable the Quad I/O mode
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// Disable the Write protection bits in the status register
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// Disable the Write protection bits in the status register
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// Chip should already be up and running, so we can start
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// Chip should already be up and running, so we can start
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// immediately ....
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// immediately ....
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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spi_wr <= 1'b0;
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spi_wr <= 1'b0;
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spi_hold <= 1'b0;
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spi_hold <= 1'b0;
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spi_spd <= 1'b0;
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spi_spd <= 1'b0;
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spi_dir <= 1'b0;
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spi_dir <= 1'b0;
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last_status <= 8'h00;
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last_status <= 8'h00;
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state <= `WBQSPI_RESET_QUADMODE;
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state <= `WBQSPI_RESET_QUADMODE;
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spif_req <= 1'b0;
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spif_req <= 1'b0;
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spif_override <= 1'b1;
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spif_override <= 1'b1;
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last_status <= 8'hfc; //
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last_status <= 8'hfc; //
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// This guarantees that we aren't starting in quad
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// This guarantees that we aren't starting in quad
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// I/O mode, where the FPGA configuration scripts may
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// I/O mode, where the FPGA configuration scripts may
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// have left us.
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// have left us.
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end else if (state == `WBQSPI_RESET_QUADMODE)
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end else if (state == `WBQSPI_RESET_QUADMODE)
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begin
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begin
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// Okay, so here's the problem: we don't know whether or not
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// Okay, so here's the problem: we don't know whether or not
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// the Xilinx loader started us up in Quad Read I/O idle mode.
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// the Xilinx loader started us up in Quad Read I/O idle mode.
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// So, thus we need to
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// So, thus we need to
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// Not ready to handle the bus yet, so stall any requests
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// Not ready to handle the bus yet, so stall any requests
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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// Do something ...
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// Do something ...
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if (last_status == 8'h00)
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if (last_status == 8'h00)
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begin
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begin
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spif_override <= 1'b0;
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spif_override <= 1'b0;
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state <= `WBQSPI_IDLE;
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state <= `WBQSPI_IDLE;
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end else begin
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end else begin
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last_status <= last_status - 8'h1;
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last_status <= last_status - 8'h1;
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spif_override <= 1'b1;
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spif_override <= 1'b1;
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spif_cmd <= last_status[3]; // Toggle CS_n
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spif_cmd <= last_status[3]; // Toggle CS_n
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spif_ctrl <= last_status[0]; // Toggle clock too
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spif_ctrl <= last_status[0]; // Toggle clock too
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end
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end
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end else if (state == `WBQSPI_IDLE)
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end else if (state == `WBQSPI_IDLE)
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begin
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begin
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o_interrupt <= 1'b0;
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o_interrupt <= 1'b0;
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o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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spif_cmd <= i_wb_we;
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spif_cmd <= i_wb_we;
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spif_addr <= i_wb_addr;
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spif_addr <= i_wb_addr;
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spif_data <= i_wb_data;
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spif_data <= i_wb_data;
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spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
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spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
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spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
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spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
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spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
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spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
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spi_hold <= 1'b0;
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spi_hold <= 1'b0;
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spi_spd <= 1'b0;
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spi_spd <= 1'b0;
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spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
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spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
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// Data register access
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// Data register access
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if ((i_wb_data_stb)&&(i_wb_cyc))
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if ((i_wb_data_stb)&&(i_wb_cyc))
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begin
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begin
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|
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if (i_wb_we) // Request to write a page
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if (i_wb_we) // Request to write a page
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begin
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begin
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`ifdef READ_ONLY
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o_wb_ack <= 1'b1;
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o_wb_stall <= 1'b0;
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end else
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`else
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if((~write_protect)&&(~write_in_progress))
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if((~write_protect)&&(~write_in_progress))
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begin // 00
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begin // 00
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spi_wr <= 1'b1;
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spi_wr <= 1'b1;
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spi_len <= 2'b00; // 8 bits
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spi_len <= 2'b00; // 8 bits
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// Send a write enable command
|
// Send a write enable command
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spi_in <= { 8'h06, 24'h00 };
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spi_in <= { 8'h06, 24'h00 };
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state <= `WBQSPI_WEN;
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state <= `WBQSPI_WEN;
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|
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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end else if (write_protect)
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end else if (write_protect)
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begin // whether or not write-in_progress ...
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begin // whether or not write-in_progress ...
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// Do nothing on a write protect
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// Do nothing on a write protect
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// violation
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// violation
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//
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//
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o_wb_ack <= 1'b1;
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o_wb_ack <= 1'b1;
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o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
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end else begin // write is in progress, wait
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end else begin // write is in progress, wait
|
// for it to complete
|
// for it to complete
|
state <= `WBQSPI_WAIT_WIP_CLEAR;
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state <= `WBQSPI_WAIT_WIP_CLEAR;
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o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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end
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end
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end else if (~write_in_progress)
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end else if (~write_in_progress)
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`endif
|
begin // Read access, normal mode(s)
|
begin // Read access, normal mode(s)
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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spi_wr <= 1'b1; // Write cmd to device
|
spi_wr <= 1'b1; // Write cmd to device
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if (quad_mode_enabled)
|
if (quad_mode_enabled)
|
begin
|
begin
|
spi_in <= { 8'heb, 2'b00, i_wb_addr[19:0], 2'b00 };
|
spi_in <= { 8'heb,
|
|
{(24-ADDRESS_WIDTH){1'b0}},
|
|
i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
|
state <= `WBQSPI_QRD_ADDRESS;
|
state <= `WBQSPI_QRD_ADDRESS;
|
spi_len <= 2'b00; // single byte, cmd only
|
spi_len <= 2'b00; // single byte, cmd only
|
end else begin
|
end else begin
|
spi_in <= { 8'h0b, 2'b00, i_wb_addr[19:0], 2'b00 };
|
spi_in <= { 8'h0b,
|
|
{(24-ADDRESS_WIDTH){1'b0}},
|
|
i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
|
state <= `WBQSPI_RD_DUMMY;
|
state <= `WBQSPI_RD_DUMMY;
|
spi_len <= 2'b11; // cmd+addr,32bits
|
spi_len <= 2'b11; // cmd+addr,32bits
|
end
|
end
|
|
`ifndef READ_ONLY
|
end else begin
|
end else begin
|
// A write is in progress ... need to stall
|
// A write is in progress ... need to stall
|
// the bus until the write is complete.
|
// the bus until the write is complete.
|
state <= `WBQSPI_WAIT_WIP_CLEAR;
|
state <= `WBQSPI_WAIT_WIP_CLEAR;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
`endif
|
end
|
end
|
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
|
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
|
begin
|
begin
|
|
`ifdef READ_ONLY
|
|
o_wb_ack <= 1'b1;
|
|
o_wb_stall <= 1'b0;
|
|
`else
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
case(i_wb_addr[1:0])
|
case(i_wb_addr[1:0])
|
2'b00: begin // Erase command register
|
2'b00: begin // Erase command register
|
write_protect <= ~i_wb_data[28];
|
write_protect <= ~i_wb_data[28];
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
|
|
if((i_wb_data[31])&&(~write_in_progress))
|
if((i_wb_data[31])&&(~write_in_progress))
|
begin
|
begin
|
// Command an erase--ack it immediately
|
// Command an erase--ack it immediately
|
|
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
|
|
if ((i_wb_data[31])&&(~write_protect))
|
if ((i_wb_data[31])&&(~write_protect))
|
begin
|
begin
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00;
|
spi_len <= 2'b00;
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBQSPI_ERASE_CMD;
|
state <= `WBQSPI_ERASE_CMD;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
end else if (i_wb_data[31])
|
end else if (i_wb_data[31])
|
begin
|
begin
|
state <= `WBQSPI_WAIT_WIP_CLEAR;
|
state <= `WBQSPI_WAIT_WIP_CLEAR;
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end else
|
end else
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
end
|
end
|
2'b01: begin
|
2'b01: begin
|
// Write the configuration register
|
// Write the configuration register
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
// Need to send a write enable command first
|
// Need to send a write enable command first
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00; // 8 bits
|
spi_len <= 2'b00; // 8 bits
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBQSPI_WRITE_CONFIG;
|
state <= `WBQSPI_WRITE_CONFIG;
|
end
|
end
|
2'b10: begin
|
2'b10: begin
|
// Write the status register
|
// Write the status register
|
o_wb_ack <= 1'b1; // Ack immediately
|
o_wb_ack <= 1'b1; // Ack immediately
|
o_wb_stall <= 1'b1; // Stall other cmds
|
o_wb_stall <= 1'b1; // Stall other cmds
|
// Need to send a write enable command first
|
// Need to send a write enable command first
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00; // 8 bits
|
spi_len <= 2'b00; // 8 bits
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBQSPI_WRITE_STATUS;
|
state <= `WBQSPI_WRITE_STATUS;
|
end
|
end
|
2'b11: begin // Write the ID register??? makes no sense
|
2'b11: begin // Write the ID register??? makes no sense
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
end
|
end
|
endcase
|
endcase
|
|
`endif
|
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
|
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
|
begin
|
begin
|
case(i_wb_addr[1:0])
|
case(i_wb_addr[1:0])
|
2'b00: begin // Read local register
|
2'b00: begin // Read local register
|
if (write_in_progress) // Read status
|
if (write_in_progress) // Read status
|
begin// register, is write still in progress?
|
begin// register, is write still in progress?
|
state <= `WBQSPI_READ_STATUS;
|
state <= `WBQSPI_READ_STATUS;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01;// 8 bits out, 8 bits in
|
spi_len <= 2'b01;// 8 bits out, 8 bits in
|
spi_in <= { 8'h05, 24'h00};
|
spi_in <= { 8'h05, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end else begin // Return w/o talking to device
|
end else begin // Return w/o talking to device
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_data <= { write_in_progress,
|
o_wb_data <= { write_in_progress,
|
dirty_sector, spi_busy,
|
dirty_sector, spi_busy,
|
~write_protect,
|
~write_protect,
|
quad_mode_enabled,
|
quad_mode_enabled,
|
7'h00,
|
{(29-ADDRESS_WIDTH){1'b0}},
|
erased_sector, 14'h000 };
|
erased_sector, 14'h000 };
|
end end
|
end end
|
2'b01: begin // Read configuration register
|
2'b01: begin // Read configuration register
|
state <= `WBQSPI_READ_CONFIG;
|
state <= `WBQSPI_READ_CONFIG;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01;
|
spi_len <= 2'b01;
|
spi_in <= { 8'h35, 24'h00};
|
spi_in <= { 8'h35, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
2'b10: begin // Read status register
|
2'b10: begin // Read status register
|
state <= `WBQSPI_READ_STATUS;
|
state <= `WBQSPI_READ_STATUS;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_in <= { 8'h05, 24'h00};
|
spi_in <= { 8'h05, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
2'b11: begin // Read ID register
|
2'b11: begin // Read ID register
|
state <= `WBQSPI_READ_ID_CMD;
|
state <= `WBQSPI_READ_ID_CMD;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00;
|
spi_len <= 2'b00;
|
spi_in <= { 8'h9f, 24'h00};
|
spi_in <= { 8'h9f, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
endcase
|
endcase
|
|
`ifndef READ_ONLY
|
end else if ((~i_wb_cyc)&&(write_in_progress))
|
end else if ((~i_wb_cyc)&&(write_in_progress))
|
begin
|
begin
|
state <= `WBQSPI_IDLE_CHECK_WIP;
|
state <= `WBQSPI_IDLE_CHECK_WIP;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_in <= { 8'h05, 24'h00};
|
spi_in <= { 8'h05, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
`endif
|
end
|
end
|
end else if (state == `WBQSPI_RDIDLE)
|
end else if (state == `WBQSPI_RDIDLE)
|
begin
|
begin
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spif_cmd <= i_wb_we;
|
spif_cmd <= i_wb_we;
|
spif_addr <= i_wb_addr;
|
spif_addr <= i_wb_addr;
|
spif_data <= i_wb_data;
|
spif_data <= i_wb_data;
|
spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
|
spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
|
spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
|
spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_spd<= 1'b1;
|
spi_spd<= 1'b1;
|
spi_dir <= 1'b0; // Write (for now)
|
spi_dir <= 1'b0; // Write (for now)
|
if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we))
|
if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we))
|
begin // Continue our read ... send the new address / mode
|
begin // Continue our read ... send the new address / mode
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b10; // Write address, but not mode byte
|
spi_len <= 2'b10; // Write address, but not mode byte
|
spi_in <= { 2'h0, i_wb_addr[19:0], 2'h0, 8'ha0 };
|
spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
|
|
i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
|
state <= `WBQSPI_QRD_DUMMY;
|
state <= `WBQSPI_QRD_DUMMY;
|
end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
|
end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
|
begin
|
begin
|
// A local read that doesn't touch the device, so leave
|
// A local read that doesn't touch the device, so leave
|
// the device in its current state
|
// the device in its current state
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_data <= { write_in_progress,
|
o_wb_data <= { write_in_progress,
|
dirty_sector, spi_busy,
|
dirty_sector, spi_busy,
|
~write_protect,
|
~write_protect,
|
quad_mode_enabled,
|
quad_mode_enabled,
|
7'h00,
|
{(29-ADDRESS_WIDTH){1'b0}},
|
erased_sector, 14'h000 };
|
erased_sector, 14'h000 };
|
end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb)))
|
end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb)))
|
begin // Need to release the device from quad mode for all else
|
begin // Need to release the device from quad mode for all else
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b11;
|
spi_len <= 2'b11;
|
spi_in <= 32'h00;
|
spi_in <= 32'h00;
|
state <= `WBQSPI_WBDECODE;
|
state <= `WBQSPI_WBDECODE;
|
end
|
end
|
end else if (state == `WBQSPI_WBDECODE)
|
end else if (state == `WBQSPI_WBDECODE)
|
begin
|
begin
|
// We were in quad SPI read mode, and had to get out.
|
// We were in quad SPI read mode, and had to get out.
|
// Now we've got a command (not data read) to read and
|
// Now we've got a command (not data read) to read and
|
// execute. Accomplish what we would've done while in the
|
// execute. Accomplish what we would've done while in the
|
// IDLE state here, save only that we don't have to worry
|
// IDLE state here, save only that we don't have to worry
|
// about data reads, and we need to operate on a stored
|
// about data reads, and we need to operate on a stored
|
// version of the bus command
|
// version of the bus command
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
|
spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_spd <= 1'b0;
|
spi_spd <= 1'b0;
|
spi_dir <= 1'b0;
|
spi_dir <= 1'b0;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
|
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
|
begin
|
begin
|
// Data register access
|
// Data register access
|
if (~spif_ctrl)
|
if (~spif_ctrl)
|
begin
|
begin
|
if (spif_cmd) // Request to write a page
|
if (spif_cmd) // Request to write a page
|
begin
|
begin
|
|
`ifdef READ_ONLY
|
|
o_wb_ack <= spif_req;
|
|
o_wb_stall <= 1'b0;
|
|
state <= `WBQSPI_IDLE;
|
|
`else
|
if((~write_protect)&&(~write_in_progress))
|
if((~write_protect)&&(~write_in_progress))
|
begin // 00
|
begin // 00
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00; // 8 bits
|
spi_len <= 2'b00; // 8 bits
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBQSPI_WEN;
|
state <= `WBQSPI_WEN;
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end else if (write_protect)
|
end else if (write_protect)
|
begin // whether or not write-in_progress ...
|
begin // whether or not write-in_progress ...
|
// Do nothing on a write protect
|
// Do nothing on a write protect
|
// violation
|
// violation
|
//
|
//
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
end else begin // write is in progress, wait
|
end else begin // write is in progress, wait
|
// for it to complete
|
// for it to complete
|
state <= `WBQSPI_WAIT_WIP_CLEAR;
|
state <= `WBQSPI_WAIT_WIP_CLEAR;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
// end else if (~write_in_progress) // always true
|
// end else if (~write_in_progress) // always true
|
// but ... we wouldn't get here on a normal read access
|
// but ... we wouldn't get here on a normal read access
|
|
`endif
|
end else begin
|
end else begin
|
// Something's wrong, we should never get here
|
// Something's wrong, we should never
|
|
// get here
|
// Attempt to go to idle to recover
|
// Attempt to go to idle to recover
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
end
|
end
|
end else if ((spif_ctrl)&&(spif_cmd))
|
end else if ((spif_ctrl)&&(spif_cmd))
|
begin
|
begin
|
|
`ifdef READ_ONLY
|
|
o_wb_ack <= spif_req;
|
|
o_wb_stall <= 1'b0;
|
|
state <= `WBQSPI_IDLE;
|
|
`else
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
case(spif_addr[1:0])
|
case(spif_addr[1:0])
|
2'b00: begin // Erase command register
|
2'b00: begin // Erase command register
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
write_protect <= ~spif_data[28];
|
write_protect <= ~spif_data[28];
|
// Are we commanding an erase?
|
// Are we commanding an erase?
|
// We're in read mode, writes cannot
|
// We're in read mode, writes cannot
|
// be in progress, so ...
|
// be in progress, so ...
|
if (spif_data[31]) // Command an erase
|
if (spif_data[31]) // Command an erase
|
begin
|
begin
|
// Since we're not going back
|
// Since we're not going back
|
// to IDLE, we must stall the
|
// to IDLE, we must stall the
|
// bus here
|
// bus here
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00;
|
spi_len <= 2'b00;
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBQSPI_ERASE_CMD;
|
state <= `WBQSPI_ERASE_CMD;
|
end end
|
end end
|
2'b01: begin
|
2'b01: begin
|
// Write the configuration register
|
// Write the configuration register
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
// Need to send a write enable command first
|
// Need to send a write enable command first
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00; // 8 bits
|
spi_len <= 2'b00; // 8 bits
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBQSPI_WRITE_CONFIG;
|
state <= `WBQSPI_WRITE_CONFIG;
|
end
|
end
|
2'b10: begin
|
2'b10: begin
|
// Write the status register
|
// Write the status register
|
o_wb_ack <= spif_req; // Ack immediately
|
o_wb_ack <= spif_req; // Ack immediately
|
o_wb_stall <= 1'b1; // Stall other cmds
|
o_wb_stall <= 1'b1; // Stall other cmds
|
// Need to send a write enable command first
|
// Need to send a write enable command first
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00; // 8 bits
|
spi_len <= 2'b00; // 8 bits
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBQSPI_WRITE_STATUS;
|
state <= `WBQSPI_WRITE_STATUS;
|
end
|
end
|
2'b11: begin // Write the ID register??? makes no sense
|
2'b11: begin // Write the ID register??? makes no sense
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
end
|
end
|
endcase
|
endcase
|
|
`endif
|
end else begin // on (~spif_we)
|
end else begin // on (~spif_we)
|
case(spif_addr[1:0])
|
case(spif_addr[1:0])
|
2'b00: begin // Read local register
|
2'b00: begin // Read local register
|
// Nonsense case--would've done this
|
// Nonsense case--would've done this
|
// already
|
// already
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
end
|
end
|
2'b01: begin // Read configuration register
|
2'b01: begin // Read configuration register
|
state <= `WBQSPI_READ_CONFIG;
|
state <= `WBQSPI_READ_CONFIG;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01;
|
spi_len <= 2'b01;
|
spi_in <= { 8'h35, 24'h00};
|
spi_in <= { 8'h35, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
2'b10: begin // Read status register
|
2'b10: begin // Read status register
|
state <= `WBQSPI_READ_STATUS;
|
state <= `WBQSPI_READ_STATUS;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_in <= { 8'h05, 24'h00};
|
spi_in <= { 8'h05, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
2'b11: begin // Read ID register
|
2'b11: begin // Read ID register
|
state <= `WBQSPI_READ_ID_CMD;
|
state <= `WBQSPI_READ_ID_CMD;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00;
|
spi_len <= 2'b00;
|
spi_in <= { 8'h9f, 24'h00};
|
spi_in <= { 8'h9f, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
|
//
|
begin
|
//
|
o_wb_stall <= 1'b1;
|
// READ DATA section: for both data and commands
|
o_wb_ack <= 1'b0;
|
//
|
spi_wr <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if (~spi_busy)
|
|
begin
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h05, 24'h0000 };
|
|
spi_hold <= 1'b1;
|
|
spi_len <= 2'b01; // 16 bits write, so we can read 8
|
|
state <= `WBQSPI_CHECK_WIP_CLEAR;
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
end
|
|
end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
// Repeat as often as necessary until we are clear
|
|
spi_wr <= 1'b1;
|
|
spi_in <= 32'h0000; // Values here are actually irrelevant
|
|
spi_hold <= 1'b1;
|
|
spi_len <= 2'b00; // One byte at a time
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((spi_valid)&&(~spi_out[0]))
|
|
begin
|
|
state <= `WBQSPI_CHECK_WIP_DONE;
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b0;
|
|
write_in_progress <= 1'b0;
|
|
last_status <= spi_out[7:0];
|
|
end
|
|
end else if (state == `WBQSPI_CHECK_WIP_DONE)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
// Let's let the SPI port come back to a full idle,
|
|
// and the chip select line go low before continuing
|
|
spi_wr <= 1'b0;
|
|
spi_len <= 2'b00;
|
|
spi_hold <= 1'b0;
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
|
|
begin
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b0;
|
|
|
|
casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
|
|
4'b00??: begin // Read data from ... somewhere
|
|
spi_wr <= 1'b1; // Write cmd to device
|
|
if (quad_mode_enabled)
|
|
begin
|
|
spi_in <= { 8'heb, 2'b00, spif_addr[19:0], 2'b00 };
|
|
state <= `WBQSPI_QRD_ADDRESS;
|
|
// spi_len <= 2'b00; // single byte, cmd only
|
|
end else begin
|
|
spi_in <= { 8'h0b, 2'b00, spif_addr[19:0], 2'b00 };
|
|
state <= `WBQSPI_RD_DUMMY;
|
|
spi_len <= 2'b11; // Send cmd and addr
|
|
end end
|
|
4'b10??: begin // Write data to ... anywhere
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b00; // 8 bits
|
|
// Send a write enable command
|
|
spi_in <= { 8'h06, 24'h00 };
|
|
state <= `WBQSPI_WEN;
|
|
end
|
|
4'b0110: begin // Read status register
|
|
state <= `WBQSPI_READ_STATUS;
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
|
spi_in <= { 8'h05, 24'h00};
|
|
end
|
|
4'b0111: begin
|
|
state <= `WBQSPI_READ_ID_CMD;
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b00;
|
|
spi_in <= { 8'h9f, 24'h00};
|
|
end
|
|
default: begin //
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= spif_req;
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
end
|
|
endcase
|
|
// spif_cmd <= i_wb_we;
|
|
// spif_addr <= i_wb_addr;
|
|
// spif_data <= i_wb_data;
|
|
// spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
|
|
// spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
|
|
end
|
|
end else if (state == `WBQSPI_WEN)
|
|
begin // We came here after issuing a write enable command
|
|
spi_wr <= 1'b0;
|
|
o_wb_ack <= 1'b0;
|
|
o_wb_stall <= 1'b1;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
|
|
state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
|
|
// state <= `WBQSPI_PP;
|
|
end else if (state == `WBQSPI_PP)
|
|
begin // We come here under a full stop / full port idle mode
|
|
// Issue our command immediately
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h02, 2'h0, spif_addr, 2'b00 };
|
|
spi_len <= 2'b11;
|
|
spi_hold <= 1'b1;
|
|
spi_spd <= 1'b0;
|
|
spi_dir <= 1'b0; // Writing
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
|
// Once we get busy, move on
|
|
if (spi_busy)
|
|
state <= `WBQSPI_WR_DATA;
|
|
if (spif_sector == erased_sector)
|
|
dirty_sector <= 1'b1;
|
|
end else if (state == `WBQSPI_QPP)
|
|
begin // We come here under a full stop / full port idle mode
|
|
// Issue our command immediately
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h32, 2'h0, spif_addr, 2'b00 };
|
|
spi_len <= 2'b11;
|
|
spi_hold <= 1'b1;
|
|
spi_spd <= 1'b0;
|
|
spi_dir <= 1'b0; // Writing
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
|
// Once we get busy, move on
|
|
if (spi_busy)
|
|
begin
|
|
// spi_wr is irrelevant here ...
|
|
// Set the speed value once, but wait til we get busy
|
|
// to do so.
|
|
spi_spd <= 1'b1;
|
|
state <= `WBQSPI_WR_DATA;
|
|
end
|
|
if (spif_sector == erased_sector)
|
|
dirty_sector <= 1'b1;
|
|
end else if (state == `WBQSPI_WR_DATA)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
spi_wr <= 1'b1; // write without waiting
|
|
spi_in <= {
|
|
spif_data[ 7: 0],
|
|
spif_data[15: 8],
|
|
spif_data[23:16],
|
|
spif_data[31:24] };
|
|
spi_len <= 2'b11; // Write 4 bytes
|
|
spi_hold <= 1'b1;
|
|
if (~spi_busy)
|
|
begin
|
|
o_wb_ack <= spif_req; // Ack when command given
|
|
state <= `WBQSPI_WR_BUS_CYCLE;
|
|
end
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
end else if (state == `WBQSPI_WR_BUS_CYCLE)
|
|
begin
|
|
o_wb_ack <= 1'b0; // Turn off our ack and stall flags
|
|
o_wb_stall <= 1'b1;
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b1;
|
|
write_in_progress <= 1'b1;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if (~i_wb_cyc)
|
|
begin
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
spi_hold <= 1'b0;
|
|
end else if (spi_wr)
|
|
begin // Give the SPI a chance to get busy on the last write
|
|
// Do nothing here.
|
|
end else if ((i_wb_data_stb)&&(i_wb_we)
|
|
&&(i_wb_addr == (spif_addr+1))
|
|
&&(i_wb_addr[19:6]==spif_addr[19:6]))
|
|
begin
|
|
spif_cmd <= 1'b1;
|
|
spif_data <= i_wb_data;
|
|
spif_addr <= i_wb_addr;
|
|
spif_ctrl <= 1'b0;
|
|
spif_req<= 1'b1;
|
|
// We'll keep the bus stalled on this request
|
|
// for a while
|
|
state <= `WBQSPI_WR_DATA;
|
|
o_wb_ack <= 1'b0;
|
|
o_wb_stall <= 1'b0;
|
|
end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
|
|
begin
|
|
spi_hold <= 1'b0;
|
|
spi_wr <= 1'b0;
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
end // Otherwise we stay here
|
|
end else if (state == `WBQSPI_RD_DUMMY)
|
end else if (state == `WBQSPI_RD_DUMMY)
|
begin
|
begin
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_wr <= 1'b1; // Non-stop
|
spi_wr <= 1'b1; // Non-stop
|
// Need to read one byte of dummy data,
|
// Need to read one byte of dummy data,
|
// just to consume 8 clocks
|
// just to consume 8 clocks
|
spi_in <= { 8'h00, 24'h00 };
|
spi_in <= { 8'h00, 24'h00 };
|
spi_len <= 2'b00; // Read 8 bits
|
spi_len <= 2'b00; // Read 8 bits
|
spi_spd <= 1'b0;
|
spi_spd <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
if ((~spi_busy)&&(~o_qspi_cs_n))
|
if ((~spi_busy)&&(~o_qspi_cs_n))
|
// Our command was accepted
|
// Our command was accepted
|
state <= `WBQSPI_READ_CMD;
|
state <= `WBQSPI_READ_CMD;
|
end else if (state == `WBQSPI_QRD_ADDRESS)
|
end else if (state == `WBQSPI_QRD_ADDRESS)
|
begin
|
begin
|
// We come in here immediately upon issuing a QRD read
|
// We come in here immediately upon issuing a QRD read
|
// command (8-bits), but we have to pause to give the
|
// command (8-bits), but we have to pause to give the
|
// address (24-bits) and mode (8-bits) in quad speed.
|
// address (24-bits) and mode (8-bits) in quad speed.
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_wr <= 1'b1; // Non-stop
|
spi_wr <= 1'b1; // Non-stop
|
spi_in <= { 2'b0, spif_addr, 2'b0, 8'ha0 };
|
spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
|
|
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
|
spi_len <= 2'b10; // Write address, not mode byte
|
spi_len <= 2'b10; // Write address, not mode byte
|
spi_spd <= 1'b1;
|
spi_spd <= 1'b1;
|
spi_dir <= 1'b0; // Still writing
|
spi_dir <= 1'b0; // Still writing
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
if ((~spi_busy)&&(spi_spd))
|
if ((~spi_busy)&&(spi_spd))
|
// Our command was accepted
|
// Our command was accepted
|
state <= `WBQSPI_QRD_DUMMY;
|
state <= `WBQSPI_QRD_DUMMY;
|
end else if (state == `WBQSPI_QRD_DUMMY)
|
end else if (state == `WBQSPI_QRD_DUMMY)
|
begin
|
begin
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_wr <= 1'b1; // Non-stop
|
spi_wr <= 1'b1; // Non-stop
|
spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
|
spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
|
spi_len <= 2'b10; // Write 8 bits
|
spi_len <= 2'b10; // Write 8 bits
|
spi_spd <= 1'b1;
|
spi_spd <= 1'b1;
|
spi_dir <= 1'b0; // Still writing
|
spi_dir <= 1'b0; // Still writing
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
|
if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
|
// Our command was accepted
|
// Our command was accepted
|
state <= `WBQSPI_READ_CMD;
|
state <= `WBQSPI_READ_CMD;
|
end else if (state == `WBQSPI_READ_CMD)
|
end else if (state == `WBQSPI_READ_CMD)
|
begin // Issue our first command to read 32 bits.
|
begin // Issue our first command to read 32 bits.
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_in <= { 8'hff, 24'h00 }; // Empty
|
spi_in <= { 8'hff, 24'h00 }; // Empty
|
spi_len <= 2'b11; // Read 32 bits
|
spi_len <= 2'b11; // Read 32 bits
|
spi_dir <= 1'b1; // Now reading
|
spi_dir <= 1'b1; // Now reading
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
if ((spi_valid)&&(spi_len == 2'b11))
|
if ((spi_valid)&&(spi_len == 2'b11))
|
state <= `WBQSPI_READ_DATA;
|
state <= `WBQSPI_READ_DATA;
|
end else if (state == `WBQSPI_READ_DATA)
|
end else if (state == `WBQSPI_READ_DATA)
|
begin
|
begin
|
// Pipelined read support
|
// Pipelined read support
|
spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
|
spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
|
spi_in <= 32'h00;
|
spi_in <= 32'h00;
|
spi_len <= 2'b11;
|
spi_len <= 2'b11;
|
// Don't adjust the speed here, it was set in the setup
|
// Don't adjust the speed here, it was set in the setup
|
spi_dir <= 1'b1; // Now we get to read
|
spi_dir <= 1'b1; // Now we get to read
|
// Don't let the device go to idle until the bus cycle ends.
|
// Don't let the device go to idle until the bus cycle ends.
|
// This actually prevents a *really* nasty race condition,
|
// This actually prevents a *really* nasty race condition,
|
// where the strobe comes in after the lower level device
|
// where the strobe comes in after the lower level device
|
// has decided to stop waiting. The write is then issued,
|
// has decided to stop waiting. The write is then issued,
|
// but no one is listening. By leaving the device open,
|
// but no one is listening. By leaving the device open,
|
// the device is kept in a state where a valid strobe
|
// the device is kept in a state where a valid strobe
|
// here will be useful. Of course, we don't accept
|
// here will be useful. Of course, we don't accept
|
// all commands, just reads. Further, the strobe needs
|
// all commands, just reads. Further, the strobe needs
|
// to be high for two clocks cycles without changing
|
// to be high for two clocks cycles without changing
|
// anything on the bus--one for us to notice it and pull
|
// anything on the bus--one for us to notice it and pull
|
// our head out of the sand, and a second for whoever
|
// our head out of the sand, and a second for whoever
|
// owns the bus to realize their command went through.
|
// owns the bus to realize their command went through.
|
spi_hold <= 1'b1;
|
spi_hold <= 1'b1;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
if ((spi_valid)&&(~spi_in[31]))
|
if ((spi_valid)&&(~spi_in[31]))
|
begin // Single pulse acknowledge and write data out
|
begin // Single pulse acknowledge and write data out
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= (~spi_wr);
|
o_wb_stall <= (~spi_wr);
|
// adjust endian-ness to match the PC
|
// adjust endian-ness to match the PC
|
o_wb_data <= { spi_out[7:0], spi_out[15:8],
|
o_wb_data <= { spi_out[7:0], spi_out[15:8],
|
spi_out[23:16], spi_out[31:24] };
|
spi_out[23:16], spi_out[31:24] };
|
state <= (spi_wr)?`WBQSPI_READ_DATA
|
state <= (spi_wr)?`WBQSPI_READ_DATA
|
: ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
|
: ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
|
spif_req <= spi_wr;
|
spif_req <= spi_wr;
|
spi_hold <= (~spi_wr);
|
spi_hold <= (~spi_wr);
|
if (spi_wr)
|
if (spi_wr)
|
spif_addr <= i_wb_addr;
|
spif_addr <= i_wb_addr;
|
end else if (~i_wb_cyc)
|
end else if (~i_wb_cyc)
|
begin // FAIL SAFE: If the bus cycle ends, forget why we're
|
begin // FAIL SAFE: If the bus cycle ends, forget why we're
|
// here, just go back to idle
|
// here, just go back to idle
|
state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
|
state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end else begin
|
end else begin
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
|
end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
|
begin // Wait 'til idle, but then go to fast read idle instead of full
|
begin // Wait 'til idle, but then go to fast read idle instead of full
|
spi_wr <= 1'b0; // idle
|
spi_wr <= 1'b0; // idle
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spif_req <= 1'b0;
|
spif_req <= 1'b0;
|
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
|
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
|
begin // clearing of the SPI port before moving on
|
begin // clearing of the SPI port before moving on
|
state <= `WBQSPI_RDIDLE;
|
state <= `WBQSPI_RDIDLE;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_ack <= 1'b0;// Shouldn't be acking anything here
|
o_wb_ack <= 1'b0;// Shouldn't be acking anything here
|
end
|
end
|
end else if (state == `WBQSPI_READ_ID_CMD)
|
end else if (state == `WBQSPI_READ_ID_CMD)
|
begin // We came into here immediately after issuing a 0x9f command
|
begin // We came into here immediately after issuing a 0x9f command
|
// Now we need to read 32 bits of data. Result should be
|
// Now we need to read 32 bits of data. Result should be
|
// 0x0102154d (8'h manufacture ID, 16'h device ID, followed
|
// 0x0102154d (8'h manufacture ID, 16'h device ID, followed
|
// by the number of extended bytes available 8'h4d).
|
// by the number of extended bytes available 8'h4d).
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall<= 1'b1;
|
o_wb_stall<= 1'b1;
|
|
|
spi_wr <= 1'b1; // No data to send, but need four bytes, since
|
spi_wr <= 1'b1; // No data to send, but need four bytes, since
|
spi_len <= 2'b11; // 32 bits of data are ... useful
|
spi_len <= 2'b11; // 32 bits of data are ... useful
|
spi_in <= 32'h00; // Irrelevant
|
spi_in <= 32'h00; // Irrelevant
|
spi_spd <= 1'b0; // Slow speed
|
spi_spd <= 1'b0; // Slow speed
|
spi_dir <= 1'b1; // Reading
|
spi_dir <= 1'b1; // Reading
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
|
if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
|
// Our command was accepted, now go read the result
|
// Our command was accepted, now go read the result
|
state <= `WBQSPI_READ_ID;
|
state <= `WBQSPI_READ_ID;
|
end else if (state == `WBQSPI_READ_ID)
|
end else if (state == `WBQSPI_READ_ID)
|
begin
|
begin
|
o_wb_ack <= 1'b0; // Assuming we're still waiting
|
o_wb_ack <= 1'b0; // Assuming we're still waiting
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_wr <= 1'b0; // No more writes, we've already written the cmd
|
spi_wr <= 1'b0; // No more writes, we've already written the cmd
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
|
|
// Here, we just wait until the result comes back
|
// Here, we just wait until the result comes back
|
// The problem is, the result may be the previous result.
|
// The problem is, the result may be the previous result.
|
// So we use spi_len as an indicator
|
// So we use spi_len as an indicator
|
spi_len <= 2'b00;
|
spi_len <= 2'b00;
|
if((spi_valid)&&(spi_len==2'b00))
|
if((spi_valid)&&(spi_len==2'b00))
|
begin // Put the results out as soon as possible
|
begin // Put the results out as soon as possible
|
o_wb_data <= spi_out[31:0];
|
o_wb_data <= spi_out[31:0];
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
spif_req <= 1'b0;
|
spif_req <= 1'b0;
|
end else if ((~spi_busy)&&(o_qspi_cs_n))
|
end else if ((~spi_busy)&&(o_qspi_cs_n))
|
begin
|
begin
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
end
|
end
|
end else if (state == `WBQSPI_READ_STATUS)
|
end else if (state == `WBQSPI_READ_STATUS)
|
begin // We enter after the command has been given, for now just
|
begin // We enter after the command has been given, for now just
|
// read and return
|
// read and return
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
if (spi_valid)
|
if (spi_valid)
|
begin
|
begin
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spif_req <= 1'b0;
|
spif_req <= 1'b0;
|
last_status <= spi_out[7:0];
|
last_status <= spi_out[7:0];
|
write_in_progress <= spi_out[0];
|
write_in_progress <= spi_out[0];
|
if (spif_addr[1:0] == 2'b00) // Local read, checking
|
if (spif_addr[1:0] == 2'b00) // Local read, checking
|
begin // status, 'cause we're writing
|
begin // status, 'cause we're writing
|
o_wb_data <= { spi_out[0],
|
o_wb_data <= { spi_out[0],
|
dirty_sector, spi_busy,
|
dirty_sector, spi_busy,
|
~write_protect,
|
~write_protect,
|
quad_mode_enabled,
|
quad_mode_enabled,
|
7'h00,
|
{(29-ADDRESS_WIDTH){1'b0}},
|
erased_sector, 14'h000 };
|
erased_sector, 14'h000 };
|
end else begin
|
end else begin
|
o_wb_data <= { 24'h00, spi_out[7:0] };
|
o_wb_data <= { 24'h00, spi_out[7:0] };
|
end
|
end
|
end
|
end
|
|
|
if ((~spi_busy)&&(~spi_wr))
|
if ((~spi_busy)&&(~spi_wr))
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
end else if (state == `WBQSPI_READ_CONFIG)
|
end else if (state == `WBQSPI_READ_CONFIG)
|
begin // We enter after the command has been given, for now just
|
begin // We enter after the command has been given, for now just
|
// read and return
|
// read and return
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
|
|
if (spi_valid)
|
if (spi_valid)
|
begin
|
begin
|
o_wb_data <= { 24'h00, spi_out[7:0] };
|
o_wb_data <= { 24'h00, spi_out[7:0] };
|
quad_mode_enabled <= spi_out[1];
|
quad_mode_enabled <= spi_out[1];
|
end
|
end
|
|
|
if ((~spi_busy)&&(~spi_wr))
|
if ((~spi_busy)&&(~spi_wr))
|
begin
|
begin
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
spif_req <= 1'b0;
|
spif_req <= 1'b0;
|
end
|
end
|
|
|
|
//
|
|
//
|
|
// Write/erase data section
|
|
//
|
|
`ifndef READ_ONLY
|
|
end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
spi_wr <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if (~spi_busy)
|
|
begin
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h05, 24'h0000 };
|
|
spi_hold <= 1'b1;
|
|
spi_len <= 2'b01; // 16 bits write, so we can read 8
|
|
state <= `WBQSPI_CHECK_WIP_CLEAR;
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
end
|
|
end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
// Repeat as often as necessary until we are clear
|
|
spi_wr <= 1'b1;
|
|
spi_in <= 32'h0000; // Values here are actually irrelevant
|
|
spi_hold <= 1'b1;
|
|
spi_len <= 2'b00; // One byte at a time
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((spi_valid)&&(~spi_out[0]))
|
|
begin
|
|
state <= `WBQSPI_CHECK_WIP_DONE;
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b0;
|
|
write_in_progress <= 1'b0;
|
|
last_status <= spi_out[7:0];
|
|
end
|
|
end else if (state == `WBQSPI_CHECK_WIP_DONE)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
// Let's let the SPI port come back to a full idle,
|
|
// and the chip select line go low before continuing
|
|
spi_wr <= 1'b0;
|
|
spi_len <= 2'b00;
|
|
spi_hold <= 1'b0;
|
|
spi_spd <= 1'b0; // Slow speed
|
|
spi_dir <= 1'b0;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
|
|
begin
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b0;
|
|
|
|
casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
|
|
4'b00??: begin // Read data from ... somewhere
|
|
spi_wr <= 1'b1; // Write cmd to device
|
|
if (quad_mode_enabled)
|
|
begin
|
|
spi_in <= { 8'heb,
|
|
{(24-ADDRESS_WIDTH){1'b0}},
|
|
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
|
|
state <= `WBQSPI_QRD_ADDRESS;
|
|
// spi_len <= 2'b00; // single byte, cmd only
|
|
end else begin
|
|
spi_in <= { 8'h0b,
|
|
{(24-ADDRESS_WIDTH){1'b0}},
|
|
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
|
|
state <= `WBQSPI_RD_DUMMY;
|
|
spi_len <= 2'b11; // Send cmd and addr
|
|
end end
|
|
4'b10??: begin // Write data to ... anywhere
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b00; // 8 bits
|
|
// Send a write enable command
|
|
spi_in <= { 8'h06, 24'h00 };
|
|
state <= `WBQSPI_WEN;
|
|
end
|
|
4'b0110: begin // Read status register
|
|
state <= `WBQSPI_READ_STATUS;
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
|
spi_in <= { 8'h05, 24'h00};
|
|
end
|
|
4'b0111: begin
|
|
state <= `WBQSPI_READ_ID_CMD;
|
|
spi_wr <= 1'b1;
|
|
spi_len <= 2'b00;
|
|
spi_in <= { 8'h9f, 24'h00};
|
|
end
|
|
default: begin //
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= spif_req;
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
end
|
|
endcase
|
|
// spif_cmd <= i_wb_we;
|
|
// spif_addr <= i_wb_addr;
|
|
// spif_data <= i_wb_data;
|
|
// spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
|
|
// spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
|
|
end
|
|
end else if (state == `WBQSPI_WEN)
|
|
begin // We came here after issuing a write enable command
|
|
spi_wr <= 1'b0;
|
|
o_wb_ack <= 1'b0;
|
|
o_wb_stall <= 1'b1;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
|
|
state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
|
|
// state <= `WBQSPI_PP;
|
|
end else if (state == `WBQSPI_PP)
|
|
begin // We come here under a full stop / full port idle mode
|
|
// Issue our command immediately
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h02,
|
|
{(24-ADDRESS_WIDTH){1'b0}},
|
|
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
|
|
spi_len <= 2'b11;
|
|
spi_hold <= 1'b1;
|
|
spi_spd <= 1'b0;
|
|
spi_dir <= 1'b0; // Writing
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
|
// Once we get busy, move on
|
|
if (spi_busy)
|
|
state <= `WBQSPI_WR_DATA;
|
|
if (spif_sector == erased_sector)
|
|
dirty_sector <= 1'b1;
|
|
end else if (state == `WBQSPI_QPP)
|
|
begin // We come here under a full stop / full port idle mode
|
|
// Issue our command immediately
|
|
spi_wr <= 1'b1;
|
|
spi_in <= { 8'h32,
|
|
{(24-ADDRESS_WIDTH){1'b0}},
|
|
spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
|
|
spi_len <= 2'b11;
|
|
spi_hold <= 1'b1;
|
|
spi_spd <= 1'b0;
|
|
spi_dir <= 1'b0; // Writing
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
|
// Once we get busy, move on
|
|
if (spi_busy)
|
|
begin
|
|
// spi_wr is irrelevant here ...
|
|
// Set the speed value once, but wait til we get busy
|
|
// to do so.
|
|
spi_spd <= 1'b1;
|
|
state <= `WBQSPI_WR_DATA;
|
|
end
|
|
if (spif_sector == erased_sector)
|
|
dirty_sector <= 1'b1;
|
|
end else if (state == `WBQSPI_WR_DATA)
|
|
begin
|
|
o_wb_stall <= 1'b1;
|
|
o_wb_ack <= 1'b0;
|
|
spi_wr <= 1'b1; // write without waiting
|
|
spi_in <= {
|
|
spif_data[ 7: 0],
|
|
spif_data[15: 8],
|
|
spif_data[23:16],
|
|
spif_data[31:24] };
|
|
spi_len <= 2'b11; // Write 4 bytes
|
|
spi_hold <= 1'b1;
|
|
if (~spi_busy)
|
|
begin
|
|
o_wb_ack <= spif_req; // Ack when command given
|
|
state <= `WBQSPI_WR_BUS_CYCLE;
|
|
end
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
end else if (state == `WBQSPI_WR_BUS_CYCLE)
|
|
begin
|
|
o_wb_ack <= 1'b0; // Turn off our ack and stall flags
|
|
o_wb_stall <= 1'b1;
|
|
spi_wr <= 1'b0;
|
|
spi_hold <= 1'b1;
|
|
write_in_progress <= 1'b1;
|
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
if (~i_wb_cyc)
|
|
begin
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
spi_hold <= 1'b0;
|
|
end else if (spi_wr)
|
|
begin // Give the SPI a chance to get busy on the last write
|
|
// Do nothing here.
|
|
end else if ((i_wb_data_stb)&&(i_wb_we)
|
|
&&(i_wb_addr == (spif_addr+1))
|
|
&&(i_wb_addr[(ADDRESS_WIDTH-3):6]==spif_addr[(ADDRESS_WIDTH-3):6]))
|
|
begin
|
|
spif_cmd <= 1'b1;
|
|
spif_data <= i_wb_data;
|
|
spif_addr <= i_wb_addr;
|
|
spif_ctrl <= 1'b0;
|
|
spif_req<= 1'b1;
|
|
// We'll keep the bus stalled on this request
|
|
// for a while
|
|
state <= `WBQSPI_WR_DATA;
|
|
o_wb_ack <= 1'b0;
|
|
o_wb_stall <= 1'b0;
|
|
end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
|
|
begin
|
|
spi_hold <= 1'b0;
|
|
spi_wr <= 1'b0;
|
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
|
end // Otherwise we stay here
|
end else if (state == `WBQSPI_WRITE_CONFIG)
|
end else if (state == `WBQSPI_WRITE_CONFIG)
|
begin // We enter immediately after commanding a WEN
|
begin // We enter immediately after commanding a WEN
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_len <= 2'b10;
|
spi_len <= 2'b10;
|
spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
|
spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
if ((~spi_busy)&&(~spi_wr))
|
if ((~spi_busy)&&(~spi_wr))
|
begin
|
begin
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
write_in_progress <= 1'b1;
|
write_in_progress <= 1'b1;
|
quad_mode_enabled <= spif_data[1];
|
quad_mode_enabled <= spif_data[1];
|
end
|
end
|
end else if (state == `WBQSPI_WRITE_STATUS)
|
end else if (state == `WBQSPI_WRITE_STATUS)
|
begin // We enter immediately after commanding a WEN
|
begin // We enter immediately after commanding a WEN
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_len <= 2'b01;
|
spi_len <= 2'b01;
|
spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
|
spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
|
// last_status <= i_wb_data[7:0]; // We'll read this in a moment
|
// last_status <= i_wb_data[7:0]; // We'll read this in a moment
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
if ((~spi_busy)&&(~spi_wr))
|
if ((~spi_busy)&&(~spi_wr))
|
begin
|
begin
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
last_status <= spif_data[7:0];
|
last_status <= spif_data[7:0];
|
write_in_progress <= 1'b1;
|
write_in_progress <= 1'b1;
|
if(((last_status[6])||(last_status[5]))
|
if(((last_status[6])||(last_status[5]))
|
&&((~spif_data[6])&&(~spif_data[5])))
|
&&((~spif_data[6])&&(~spif_data[5])))
|
state <= `WBQSPI_CLEAR_STATUS;
|
state <= `WBQSPI_CLEAR_STATUS;
|
else
|
else
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
end
|
end
|
end else if (state == `WBQSPI_ERASE_CMD)
|
end else if (state == `WBQSPI_ERASE_CMD)
|
begin // Know that WIP is clear on entry, WEN has just been commanded
|
begin // Know that WIP is clear on entry, WEN has just been commanded
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_spd <= 1'b0;
|
spi_spd <= 1'b0;
|
spi_dir <= 1'b0;
|
spi_dir <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
|
|
// Here's the erase command
|
// Here's the erase command
|
spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
|
spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
|
spi_len <= 2'b11; // 32 bit write
|
spi_len <= 2'b11; // 32 bit write
|
// together with setting our copy of the WIP bit
|
// together with setting our copy of the WIP bit
|
write_in_progress <= 1'b1;
|
write_in_progress <= 1'b1;
|
// keeping track of which sector we just erased
|
// keeping track of which sector we just erased
|
erased_sector <= spif_data[19:14];
|
erased_sector <= spif_data[(ADDRESS_WIDTH-3):14];
|
// and marking this erase sector as no longer dirty
|
// and marking this erase sector as no longer dirty
|
dirty_sector <= 1'b0;
|
dirty_sector <= 1'b0;
|
|
|
// Wait for a full stop before issuing this command
|
// Wait for a full stop before issuing this command
|
if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
|
if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
|
begin // When our command is accepted, move to the next state
|
begin // When our command is accepted, move to the next state
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
state <= `WBQSPI_ERASE_BLOCK;
|
state <= `WBQSPI_ERASE_BLOCK;
|
end
|
end
|
end else if (state == `WBQSPI_ERASE_BLOCK)
|
end else if (state == `WBQSPI_ERASE_BLOCK)
|
begin
|
begin
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
// When the port clears, we can head back to idle
|
// When the port clears, we can head back to idle
|
if ((~spi_busy)&&(~spi_wr))
|
if ((~spi_busy)&&(~spi_wr))
|
begin
|
begin
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
end
|
end
|
end else if (state == `WBQSPI_CLEAR_STATUS)
|
end else if (state == `WBQSPI_CLEAR_STATUS)
|
begin // Issue a clear status command
|
begin // Issue a clear status command
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_len <= 2'b00; // 8 bit command
|
spi_len <= 2'b00; // 8 bit command
|
spi_in <= { 8'h30, 24'h00 };
|
spi_in <= { 8'h30, 24'h00 };
|
spi_spd <= 1'b0;
|
spi_spd <= 1'b0;
|
spi_dir <= 1'b0;
|
spi_dir <= 1'b0;
|
last_status[6:5] <= 2'b00;
|
last_status[6:5] <= 2'b00;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
if ((spi_wr)&&(~spi_busy))
|
if ((spi_wr)&&(~spi_busy))
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
state <= `WBQSPI_WAIT_TIL_IDLE;
|
end else if (state == `WBQSPI_IDLE_CHECK_WIP)
|
end else if (state == `WBQSPI_IDLE_CHECK_WIP)
|
begin // We are now in read status register mode
|
begin // We are now in read status register mode
|
|
|
// No bus commands have (yet) been given
|
// No bus commands have (yet) been given
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
|
|
// Stay in this mode unless/until we get a command, or
|
// Stay in this mode unless/until we get a command, or
|
// the write is over
|
// the write is over
|
spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
|
spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
|
&&(write_in_progress));
|
&&(write_in_progress));
|
spi_len <= 2'b00; // 8 bit reads
|
spi_len <= 2'b00; // 8 bit reads
|
spi_spd <= 1'b0; // SPI, not quad
|
spi_spd <= 1'b0; // SPI, not quad
|
spi_dir <= 1'b1; // Read
|
spi_dir <= 1'b1; // Read
|
if (spi_valid)
|
if (spi_valid)
|
begin
|
begin
|
write_in_progress <= spi_out[0];
|
write_in_progress <= spi_out[0];
|
if ((~spi_out[0])&&(write_in_progress))
|
if ((~spi_out[0])&&(write_in_progress))
|
o_interrupt <= 1'b1;
|
o_interrupt <= 1'b1;
|
end else
|
end else
|
o_interrupt <= 1'b0;
|
o_interrupt <= 1'b0;
|
|
|
if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
|
if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
|
begin // We can now go to idle and process a command
|
begin // We can now go to idle and process a command
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
end
|
end
|
|
`endif // !READ_ONLY
|
end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
|
end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
|
begin
|
begin
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spif_req <= 1'b0;
|
spif_req <= 1'b0;
|
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
|
if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
|
begin // clearing of the SPI port before moving on
|
begin // clearing of the SPI port before moving on
|
state <= `WBQSPI_IDLE;
|
state <= `WBQSPI_IDLE;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_ack <= 1'b0; // Shouldn't be acking anything here
|
o_wb_ack <= 1'b0; // Shouldn't be acking anything here
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// Command and control during the reset sequence
|
// Command and control during the reset sequence
|
assign o_qspi_cs_n = (spif_override)?spif_cmd :w_qspi_cs_n;
|
assign o_qspi_cs_n = (spif_override)?spif_cmd :w_qspi_cs_n;
|
assign o_qspi_sck = (spif_override)?spif_ctrl:w_qspi_sck;
|
assign o_qspi_sck = (spif_override)?spif_ctrl:w_qspi_sck;
|
assign o_qspi_mod = (spif_override)? 2'b01 :w_qspi_mod;
|
assign o_qspi_mod = (spif_override)? 2'b01 :w_qspi_mod;
|
assign o_qspi_dat = (spif_override)? 4'b00 :w_qspi_dat;
|
assign o_qspi_dat = (spif_override)? 4'b00 :w_qspi_dat;
|
endmodule
|
endmodule
|
|
|
