<##//////////////////////////////////////////////////////////////////
|
<##//////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Author: Eyal Hochberg ////
|
//// Author: Eyal Hochberg ////
|
//// eyal@provartec.com ////
|
//// eyal@provartec.com ////
|
//// ////
|
//// ////
|
//// Downloaded from: http://www.opencores.org ////
|
//// Downloaded from: http://www.opencores.org ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Provartec LTD ////
|
//// Copyright (C) 2010 Provartec LTD ////
|
//// www.provartec.com ////
|
//// www.provartec.com ////
|
//// info@provartec.com ////
|
//// info@provartec.com ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation.////
|
//// Public License as published by the Free Software Foundation.////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more////
|
//// PURPOSE. See the GNU Lesser General Public License for more////
|
//// details. http://www.gnu.org/licenses/lgpl.html ////
|
//// details. http://www.gnu.org/licenses/lgpl.html ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////##>
|
//////////////////////////////////////////////////////////////////##>
|
|
|
##Static defines
|
|
SWAP.GLOBAL MODEL_NAME AXI interconnect fabric
|
SWAP.GLOBAL MODEL_NAME AXI interconnect fabric
|
|
|
SWAP MSTRS MASTER_NUM
|
SWAP MSTRS MASTER_NUM
|
SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))
|
SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))
|
|
|
LOOP MX MSTRS
|
LOOP MX MSTRS
|
LOOP SX SLVS
|
LOOP SX SLVS
|
|
|
SWAP MSTR_BITS LOG2(MSTRS)
|
SWAP MSTR_BITS LOG2(MSTRS)
|
SWAP SLV_BITS LOG2(SLVS)
|
SWAP SLV_BITS LOG2(SLVS)
|
|
|
SWAP SERR EXPR(SLVS-1)
|
SWAP SERR EXPR(SLVS-1)
|
|
|
GROUP IC_AXI_A is {
|
GROUP IC_AXI_A is {
|
ID ID_BITS input
|
ID ID_BITS input
|
ADDR ADDR_BITS input
|
ADDR ADDR_BITS input
|
LEN 4 input
|
LEN 4 input
|
SIZE 2 input
|
SIZE 2 input
|
BURST 2 input
|
BURST 2 input
|
CACHE 4 input
|
CACHE 4 input
|
PROT 3 input
|
PROT 3 input
|
LOCK 2 input
|
LOCK 2 input
|
USER USER_BITS input
|
USER USER_BITS input
|
VALID 1 input
|
VALID 1 input
|
READY 1 output
|
READY 1 output
|
}
|
}
|
|
|
GROUP IC_AXI_W is {
|
GROUP IC_AXI_W is {
|
ID ID_BITS input
|
ID ID_BITS input
|
DATA DATA_BITS input
|
DATA DATA_BITS input
|
STRB DATA_BITS/8 input
|
STRB DATA_BITS/8 input
|
LAST 1 input
|
LAST 1 input
|
USER USER_BITS input
|
USER USER_BITS input
|
VALID 1 input
|
VALID 1 input
|
READY 1 output
|
READY 1 output
|
}
|
}
|
|
|
GROUP IC_AXI_B is {
|
GROUP IC_AXI_B is {
|
ID ID_BITS output
|
ID ID_BITS output
|
RESP 2 output
|
RESP 2 output
|
USER USER_BITS output
|
USER USER_BITS output
|
VALID 1 output
|
VALID 1 output
|
READY 1 input
|
READY 1 input
|
}
|
}
|
|
|
GROUP IC_AXI_R is {
|
GROUP IC_AXI_R is {
|
ID ID_BITS output
|
ID ID_BITS output
|
DATA DATA_BITS output
|
DATA DATA_BITS output
|
RESP 2 output
|
RESP 2 output
|
LAST 1 output
|
LAST 1 output
|
USER USER_BITS output
|
USER USER_BITS output
|
VALID 1 output
|
VALID 1 output
|
READY 1 input
|
READY 1 input
|
}
|
}
|
|
|
GROUP IC_AXI joins {
|
GROUP IC_AXI joins {
|
GROUP IC_AXI_A prefix_AW
|
GROUP IC_AXI_A prefix_AW
|
GROUP IC_AXI_W prefix_W
|
GROUP IC_AXI_W prefix_W
|
GROUP IC_AXI_B prefix_B
|
GROUP IC_AXI_B prefix_B
|
GROUP IC_AXI_A prefix_AR
|
GROUP IC_AXI_A prefix_AR
|
GROUP IC_AXI_R prefix_R
|
GROUP IC_AXI_R prefix_R
|
}
|
}
|
|
|
GROUP IC_AXI_CMD is {
|
GROUP IC_AXI_CMD is {
|
SLV SLV_BITS input
|
SLV SLV_BITS input
|
ID ID_BITS input
|
ID ID_BITS input
|
VALID 1 input
|
VALID 1 input
|
READY 1 input
|
READY 1 input
|
}
|
}
|
|
|
