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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [def_ic_static.txt] - Diff between revs 18 and 19

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Rev 18 Rev 19
Line 38... Line 38...
SWAP MSTR_BITS LOG2(MSTRS)
SWAP MSTR_BITS LOG2(MSTRS)
SWAP SLV_BITS  LOG2(SLVS)
SWAP SLV_BITS  LOG2(SLVS)
 
 
SWAP SERR EXPR(SLVS-1)
SWAP SERR EXPR(SLVS-1)
 
 
 
IFDEF UNIQUE_ID
 
SWAP ID_BITS  MSTR_ID_BITS
 
SWAP ADD_ID   NULL
 
ELSE UNIQUE_ID
 
SWAP ID_BITS  EXPR(MSTR_ID_BITS+EXTRA_BITS)
 
SWAP ADD_ID   BIN(MX MSTR_BITS NOPRE)_
 
ENDIF UNIQUE_ID
 
 
GROUP IC_AXI_A is {
GROUP IC_AXI_A is {
    ID       ID_BITS                input
    ID       ID_BITS                input  SON(CHANGE 1)
    ADDR     ADDR_BITS              input
    ADDR     ADDR_BITS              input
    LEN      4                      input
    LEN      4                      input
    SIZE     2                      input
    SIZE     2                      input
    BURST    2                      input
    BURST    2                      input
    CACHE    4                      input
    CACHE    4                      input
Line 53... Line 61...
    VALID    1                      input
    VALID    1                      input
    READY    1                      output
    READY    1                      output
}
}
 
 
GROUP IC_AXI_W is {
GROUP IC_AXI_W is {
    ID        ID_BITS                input
    ID        ID_BITS                input  SON(CHANGE 1)
    DATA      DATA_BITS              input
    DATA      DATA_BITS              input
    STRB      DATA_BITS/8            input
    STRB      DATA_BITS/8            input
    LAST      1                      input
    LAST      1                      input
    USER      USER_BITS              input
    USER      USER_BITS              input
    VALID     1                      input
    VALID     1                      input
    READY     1                      output
    READY     1                      output
}
}
 
 
GROUP IC_AXI_B is {
GROUP IC_AXI_B is {
    ID        ID_BITS                output
    ID        ID_BITS                output  SON(CHANGE 1)
    RESP      2                      output
    RESP      2                      output
    USER      USER_BITS              output
    USER      USER_BITS              output
    VALID     1                      output
    VALID     1                      output
    READY     1                      input
    READY     1                      input
}
}
 
 
GROUP IC_AXI_R is {
GROUP IC_AXI_R is {
    ID        ID_BITS                output
    ID        ID_BITS                output  SON(CHANGE 1)
    DATA      DATA_BITS              output
    DATA      DATA_BITS              output
    RESP      2                      output
    RESP      2                      output
    LAST      1                      output
    LAST      1                      output
    USER      USER_BITS              output
    USER      USER_BITS              output
    VALID     1                      output
    VALID     1                      output
Line 90... Line 98...
    GROUP IC_AXI_R prefix_R
    GROUP IC_AXI_R prefix_R
}
}
 
 
GROUP IC_AXI_CMD is {
GROUP IC_AXI_CMD is {
    SLV       SLV_BITS               input
    SLV       SLV_BITS               input
    ID        ID_BITS                input
    ID        ID_BITS                input  SON(CHANGE 1)
    VALID     1                      input
    VALID     1                      input
    READY     1                      input
    READY     1                      input
}
}

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