| Line 60... |
Line 60... |
wire signed [15:0] sb = b;
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wire signed [15:0] sb = b;
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wire signed [7:0] als = a[7:0];
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wire signed [7:0] als = a[7:0];
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wire signed [7:0] bls = b[7:0];
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wire signed [7:0] bls = b[7:0];
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wire signed [15:0] p = als * bls;
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wire signed [15:0] p = als * bls;
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wire signed [31:0] wp = sa * sb;
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wire signed [31:0] wp = sa * sb;
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wire [15:0] p16 = a[7:0] * b[7:0];
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wire [31:0] p32 = a * b;
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// Compute AL/10
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// Compute AL/10
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// - multiply by 1/10 = 26/256
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// - multiply by 1/10 = 26/256
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wire [15:0] al26 = {al,4'b0} + {al,3'b0} + {al,1'b0}; // * 26
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wire [15:0] al26 = {al,4'b0} + {al,3'b0} + {al,1'b0}; // * 26
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wire [7:0] aldv10 = al26[15:8]; // 256
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wire [7:0] aldv10 = al26[15:8]; // 256
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| Line 83... |
Line 85... |
wire [15:0] shruo8 = {b[7:0],8'h00} >> shftamt;
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wire [15:0] shruo8 = {b[7:0],8'h00} >> shftamt;
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wire [ 7:0] shro8 = ~(~b[7:0] >> shftamt);
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wire [ 7:0] shro8 = ~(~b[7:0] >> shftamt);
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wire [16:0] shlco8 = {8'h00,b,cf} << shftamt;
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wire [16:0] shlco8 = {8'h00,b,cf} << shftamt;
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wire [16:0] shrcuo8 = {cf,b[7:0],8'h00} >> shftamt;
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wire [16:0] shrcuo8 = {cf,b[7:0],8'h00} >> shftamt;
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wire div16_done;
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wire div32_done;
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wire [15:0] q16;
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wire [7:0] r16;
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wire [31:0] q32;
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wire [15:0] r32;
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wire [31:0] negdxax = -{dx,ax};
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divr2 #(16) udiv1
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(
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.rst(rst_i),
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.clk(clk_i),
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.ce(1'b1),
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.ld(ld_div16),
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.su(TTT[0]),
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.ri(1'b0),
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.a(ax),
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.b(b[7:0]),
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.i(8'h00),
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.q(q16),
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.r(r16),
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.divByZero(),
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.done(div16_done)
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);
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divr2 #(32) udiv2
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(
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.rst(rst_i),
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.clk(clk_i),
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.ce(1'b1),
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.ld(ld_div32),
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.su(TTT[0]),
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.ri(1'b0),
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.a({dx,ax}),
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.b(b),
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.i(16'h0000),
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.q(q32),
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.r(r32),
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.divByZero(),
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.done(div32_done)
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);
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always @(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)
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always @(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)
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begin
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begin
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casex(ir)
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casex(ir)
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`MOV_M2AL,`MOV_M2AX,`LDS,`LES:
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`MOV_M2AL,`MOV_M2AX,`LDS,`LES:
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| Line 102... |
Line 147... |
`ADD,`ADD_ALI8,`ADD_AXI16: alu_o <= a + b;
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`ADD,`ADD_ALI8,`ADD_AXI16: alu_o <= a + b;
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`SUB,`SUB_ALI8,`SUB_AXI16: alu_o <= a - b;
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`SUB,`SUB_ALI8,`SUB_AXI16: alu_o <= a - b;
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`ADC,`ADC_ALI8,`ADC_AXI16: alu_o <= a + b + cf;
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`ADC,`ADC_ALI8,`ADC_AXI16: alu_o <= a + b + cf;
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`SBB,`SBB_ALI8,`SBB_AXI16: alu_o <= a - b - cf;
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`SBB,`SBB_ALI8,`SBB_AXI16: alu_o <= a - b - cf;
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`AND,`AND_ALI8,`AND_AXI16: alu_o <= a & b;
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`AND,`AND_ALI8,`AND_AXI16: alu_o <= a & b;
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`TEST,`TEST_ALI8,`TEST_AXI16: alu_o <= a & b;
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`OR, `OR_ALI8, `OR_AXI16: alu_o <= a | b;
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`OR, `OR_ALI8, `OR_AXI16: alu_o <= a | b;
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`XOR,`XOR_ALI8,`XOR_AXI16: alu_o <= a ^ b;
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`XOR,`XOR_ALI8,`XOR_AXI16: alu_o <= a ^ b;
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`CMP,`CMP_ALI8,`CMP_AXI16: alu_o <= a - b;
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`CMP,`CMP_ALI8,`CMP_AXI16: alu_o <= a - b;
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`SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
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`SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
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`INC_REG: alu_o <= a + 16'd1;
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`INC_REG: alu_o <= a + 16'd1;
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| Line 132... |
Line 178... |
3'd4: alu_o <= a & b; // AND
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3'd4: alu_o <= a & b; // AND
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3'd5: alu_o <= a - b; // SUB
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3'd5: alu_o <= a - b; // SUB
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3'd6: alu_o <= a ^ b; // XOR
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3'd6: alu_o <= a ^ b; // XOR
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default: alu_o <= 16'h0000;
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default: alu_o <= 16'h0000;
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endcase
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endcase
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8'hF6,8'hF7:
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case(TTT)
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3'd0: alu_o <= a & b; // TEST
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3'd2: alu_o <= ~b; // NOT
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3'd3: alu_o <= -b; // NEG
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3'd4: alu_o <= w ? p32[15:0] : p16; // MUL
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3'd5: alu_o <= w ? wp[15:0] : p[15:0]; // IMUL
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3'd6: alu_o <= 16'h0000; // DIV
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3'd7: alu_o <= 16'h0000; // IDIV
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default: alu_o <= 16'h0000;
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endcase
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`AAA:
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`AAA:
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if (al[3:0]>4'h9 || af) begin
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if (al[3:0]>4'h9 || af) begin
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alu_o[3:0] <= al[3:0] + 4'd6;
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alu_o[3:0] <= al[3:0] + 4'd6;
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alu_o[7:4] <= 4'h0;
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alu_o[7:4] <= 4'h0;
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alu_o[15:8] <= ah + 8'd1;
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alu_o[15:8] <= ah + 8'd1;
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