//=============================================================================
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//=============================================================================
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// INTA: acknowledge interrupt
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// INTA: acknowledge interrupt
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//
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//
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//
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//
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// 2009,2010,2012 Robert Finch
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// 2009,2010,2012 Robert Finch
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// Stratford
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// Stratford
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// robfinch<remove>opencores.org
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// robfinch<remove>opencores.org
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// - issue two interrupt acknowledge cycles
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// - issue two interrupt acknowledge cycles
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// - one the second cycle load the interrupt number
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// - one the second cycle load the interrupt number
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//=============================================================================
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//=============================================================================
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//
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//
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INTA0:
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INTA0:
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begin
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begin
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cyc_type <= `CT_INTA;
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cyc_type <= `CT_INTA;
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inta_o <= 1'b1;
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inta_o <= 1'b1;
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mio_o <= 1'b0;
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mio_o <= 1'b0;
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lock_o <= 1'b1;
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lock_o <= 1'b1;
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b0;
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we_o <= 1'b0;
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state <= INTA1;
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state <= INTA1;
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end
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end
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INTA1:
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INTA1:
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if (ack_i) begin
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if (ack_i) begin
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cyc_type <= `CT_PASSIVE;
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cyc_type <= `CT_PASSIVE;
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mio_o <= 1'b1;
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mio_o <= 1'b1;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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state <= INTA2;
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state <= INTA2;
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end
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end
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INTA2:
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INTA2:
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begin
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begin
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cyc_type <= `CT_INTA;
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cyc_type <= `CT_INTA;
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mio_o <= 1'b0;
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mio_o <= 1'b0;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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state <= INTA3;
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state <= INTA3;
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end
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end
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INTA3:
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INTA3:
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if (ack_i) begin
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if (ack_i) begin
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cyc_type <= `CT_PASSIVE;
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cyc_type <= `CT_PASSIVE;
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inta_o <= 1'b0;
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inta_o <= 1'b0;
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mio_o <= 1'b1;
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mio_o <= 1'b1;
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lock_o <= 1'b0;
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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int_num <= dat_i;
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int_num <= dat_i;
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state <= INT1;
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state <= INT2;
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end
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end
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