OpenCores

Rev 3	Rev 4
Line 25...	Line 25...
`// Webpack 9.2i xc3s1000 4-ft256`	`// Webpack 9.2i xc3s1000 4-ft256`
`// 2550 slices / 4900 LUTs / 61 MHz`	`// 2550 slices / 4900 LUTs / 61 MHz`
`// 650 ff's / 2 MULTs`	`// 650 ff's / 2 MULTs`
`//`	`//`
`// Webpack 14.3 xc6slx45 3-csg324`	`// Webpack 14.3 xc6slx45 3-csg324`
`// 701 ff's 4115 LUTs / 90.261 MHz`	`// 736 ff's 4433 LUTs / 90.360 MHz`
`// ============================================================================`	`// ============================================================================`

//`define BYTES_ONLY 1'b1	//`define BYTES_ONLY 1'b1

//`define BIG_SEGS	//`define BIG_SEGS
Line 662...	Line 662...
`wire resz;`	`wire resz;`

`reg [2:0] cyc_type; // type of bus sycle`	`reg [2:0] cyc_type; // type of bus sycle`
`reg w; // 0=8 bit, 1=16 bit`	`reg w; // 0=8 bit, 1=16 bit`
`reg d;`	`reg d;`
	`reg v; // 1=count in cl, 0 = count is one`
`reg [1:0] mod;`	`reg [1:0] mod;`
`reg [2:0] rrr;`	`reg [2:0] rrr;`
`reg [2:0] rm;`	`reg [2:0] rm;`
`reg sxi;`	`reg sxi;`
`reg [2:0] sreg;`	`reg [2:0] sreg;`
Line 686...	Line 687...
`reg [6:0] cnt; // counter`	`reg [6:0] cnt; // counter`
`reg [1:0] S43;`	`reg [1:0] S43;`
`reg wrregs;`	`reg wrregs;`
`reg wrsregs;`	`reg wrsregs;`
`wire take_br;`	`wire take_br;`
	`reg [3:0] shftamt;`

`reg nmi_armed;`	`reg nmi_armed;`
`reg rst_nmi; // reset the nmi flag`	`reg rst_nmi; // reset the nmi flag`
`wire pe_nmi; // indicates positive edge on nmi signal`	`wire pe_nmi; // indicates positive edge on nmi signal`

Line 25...

//  Webpack 9.2i xc3s1000 4-ft256

//  Webpack 9.2i xc3s1000 4-ft256

//  2550 slices / 4900 LUTs / 61 MHz

//  2550 slices / 4900 LUTs / 61 MHz

//  650 ff's / 2 MULTs

//  650 ff's / 2 MULTs

//

//

//  Webpack 14.3  xc6slx45 3-csg324

//  Webpack 14.3  xc6slx45 3-csg324

//  701 ff's 4115 LUTs / 90.261 MHz

//  736 ff's 4433 LUTs / 90.360 MHz

// ============================================================================

// ============================================================================

//`define BYTES_ONLY    1'b1

//`define BYTES_ONLY    1'b1

//`define BIG_SEGS

//`define BIG_SEGS

Line 662...

wire resz;

wire resz;

reg [2:0] cyc_type;                      // type of bus sycle

reg [2:0] cyc_type;                      // type of bus sycle

reg w;                                          // 0=8 bit, 1=16 bit

reg w;                                          // 0=8 bit, 1=16 bit

reg d;

reg d;

reg v;                                          // 1=count in cl, 0 = count is one

reg [1:0] mod;

reg [1:0] mod;

reg [2:0] rrr;

reg [2:0] rrr;

reg [2:0] rm;

reg [2:0] rm;

reg sxi;

reg sxi;

reg [2:0] sreg;

reg [2:0] sreg;

Line 686...

Line 687...

reg [6:0] cnt;                           // counter

reg [6:0] cnt;                           // counter

reg [1:0] S43;

reg [1:0] S43;

reg wrregs;

reg wrregs;

reg wrsregs;

reg wrsregs;

wire take_br;

wire take_br;

reg [3:0] shftamt;

reg nmi_armed;

reg nmi_armed;

reg rst_nmi;                            // reset the nmi flag

reg rst_nmi;                            // reset the nmi flag

wire pe_nmi;                            // indicates positive edge on nmi signal

wire pe_nmi;                            // indicates positive edge on nmi signal

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