OpenCores

Rev 4	Rev 6
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`// Webpack 9.2i xc3s1000 4-ft256`	`// Webpack 9.2i xc3s1000 4-ft256`
`// 2550 slices / 4900 LUTs / 61 MHz`	`// 2550 slices / 4900 LUTs / 61 MHz`
`// 650 ff's / 2 MULTs`	`// 650 ff's / 2 MULTs`
`//`	`//`
`// Webpack 14.3 xc6slx45 3-csg324`	`// Webpack 14.3 xc6slx45 3-csg324`
`// 736 ff's 4433 LUTs / 90.360 MHz`	`// 884 ff's 5064 LUTs / 79.788 MHz`
`// ============================================================================`	`// ============================================================================`

//`define BYTES_ONLY 1'b1	//`define BYTES_ONLY 1'b1

//`define BIG_SEGS	//`define BIG_SEGS
Line 208...	Line 208...

`define MOVSB 8'hA4	`define MOVSB 8'hA4
`define MOVSW 8'hA5	`define MOVSW 8'hA5
`define CMPSB 8'hA6	`define CMPSB 8'hA6
`define CMPSW 8'hA7	`define CMPSW 8'hA7
	`define TEST_ALI8 8'hA8
	`define TEST_AXI16 8'hA9
`define STOSB 8'hAA	`define STOSB 8'hAA
`define STOSW 8'hAB	`define STOSW 8'hAB
`define LODSB 8'hAC	`define LODSB 8'hAC
`define LODSW 8'hAD	`define LODSW 8'hAD
`define SCASB 8'hAE	`define SCASB 8'hAE
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`000 = TEST`	`000 = TEST`
`001 =`	`001 =`
`010 = NOT`	`010 = NOT`
`011 = NEG`	`011 = NEG`
`100 = MUL`	`100 = MUL`
`101 =`	`101 = IMUL`
`110 =`	`110 = DIV`
`111 =`	`111 = IDIV`
`*/`	`*/`
`define ADDRESS_INACTIVE 20'hFFFFF	`define ADDRESS_INACTIVE 20'hFFFFF
`define DATA_INACTIVE 8'hFF	`define DATA_INACTIVE 8'hFF

`include "cycle_types.v"	`include "cycle_types.v"
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`parameter CALL_FIN1 = 8'd211;`	`parameter CALL_FIN1 = 8'd211;`
`parameter CALL_FIN2 = 8'd212;`	`parameter CALL_FIN2 = 8'd212;`
`parameter CALL_FIN3 = 8'd213;`	`parameter CALL_FIN3 = 8'd213;`
`parameter CALL_FIN4 = 8'd214;`	`parameter CALL_FIN4 = 8'd214;`

	`parameter DIVIDE1 = 8'd215;`
	`parameter DIVIDE1a = 8'd216;`
	`parameter DIVIDE2 = 8'd217;`
	`parameter DIVIDE2a = 8'd218;`
	`parameter DIVIDE3 = 8'd219;`

`parameter INT = 8'd220;`	`parameter INT = 8'd220;`
`parameter INT1 = 8'd221;`	`parameter INT1 = 8'd221;`
`parameter INT2 = 8'd222;`	`parameter INT2 = 8'd222;`
`parameter INT3 = 8'd223;`	`parameter INT3 = 8'd223;`
`parameter INT4 = 8'd224;`	`parameter INT4 = 8'd224;`
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`reg [1:0] S43;`	`reg [1:0] S43;`
`reg wrregs;`	`reg wrregs;`
`reg wrsregs;`	`reg wrsregs;`
`wire take_br;`	`wire take_br;`
`reg [3:0] shftamt;`	`reg [3:0] shftamt;`
	`reg ld_div16,ld_div32; // load divider`
	`reg div_sign;`

`reg nmi_armed;`	`reg nmi_armed;`
`reg rst_nmi; // reset the nmi flag`	`reg rst_nmi; // reset the nmi flag`
`wire pe_nmi; // indicates positive edge on nmi signal`	`wire pe_nmi; // indicates positive edge on nmi signal`

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`include "REGFILE.v"	`include "REGFILE.v"
`include "CONTROL_LOGIC.v"	`include "CONTROL_LOGIC.v"
`include "which_seg.v"	`include "which_seg.v"
`evaluate_branch u4 (ir,cx,zf,cf,sf,vf,pf,take_br);`	`evaluate_branch u4 (ir,cx,zf,cf,sf,vf,pf,take_br);`
`include "ALU.v"	`include "c:\cores\bcxa6\rtl\verilog\eight_bit\ALU.v"
`nmi_detector u6 (RESET, CLK, NMI, rst_nmi, pe_nmi);`	`nmi_detector u6 (RESET, CLK, NMI, rst_nmi, pe_nmi);`

`always @(posedge CLK)`	`always @(posedge CLK)`
`if (RESET) begin`	`if (RESET) begin`
`pf <= 1'b0;`	`pf <= 1'b0;`
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`prefix1 <= 8'h00;`	`prefix1 <= 8'h00;`
`prefix2 <= 8'h00;`	`prefix2 <= 8'h00;`
`rst_nmi <= 1'b1;`	`rst_nmi <= 1'b1;`
`wrregs <= 1'b0;`	`wrregs <= 1'b0;`
`wrsregs <= 1'b0;`	`wrsregs <= 1'b0;`
	`ld_div16 <= 1'b0;`
	`ld_div32 <= 1'b0;`
`state <= IFETCH;`	`state <= IFETCH;`
`end`	`end`
`else begin`	`else begin`
`rst_nmi <= 1'b0;`	`rst_nmi <= 1'b0;`
`wrregs <= 1'b0;`	`wrregs <= 1'b0;`
`wrsregs <= 1'b0;`	`wrsregs <= 1'b0;`
	`ld_div16 <= 1'b0;`
	`ld_div32 <= 1'b0;`

`include "WRITE_BACK.v"	`include "WRITE_BACK.v"

`case(state)`	`case(state)`

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`include "OUTB.v"	`include "OUTB.v"
`include "OUTW.v"	`include "OUTW.v"
`include "INSB.v"	`include "INSB.v"
`include "OUTSB.v"	`include "OUTSB.v"
`include "XCHG_MEM.v"	`include "XCHG_MEM.v"
	`include "DIVIDE.v"

`default:`	`default:`
`state <= IFETCH;`	`state <= IFETCH;`
`endcase`	`endcase`
`end`	`end`

Line 25...

//  Webpack 9.2i xc3s1000 4-ft256

//  Webpack 9.2i xc3s1000 4-ft256

//  2550 slices / 4900 LUTs / 61 MHz

//  2550 slices / 4900 LUTs / 61 MHz

//  650 ff's / 2 MULTs

//  650 ff's / 2 MULTs

//

//

//  Webpack 14.3  xc6slx45 3-csg324

//  Webpack 14.3  xc6slx45 3-csg324

//  736 ff's 4433 LUTs / 90.360 MHz

//  884 ff's 5064 LUTs / 79.788 MHz

// ============================================================================

// ============================================================================

//`define BYTES_ONLY    1'b1

//`define BYTES_ONLY    1'b1

//`define BIG_SEGS

//`define BIG_SEGS

Line 208...

`define MOVSB           8'hA4

`define MOVSB           8'hA4

`define MOVSW           8'hA5

`define MOVSW           8'hA5

`define CMPSB           8'hA6

`define CMPSB           8'hA6

`define CMPSW           8'hA7

`define CMPSW           8'hA7

`define TEST_ALI8       8'hA8

`define TEST_AXI16      8'hA9

`define STOSB           8'hAA

`define STOSB           8'hAA

`define STOSW           8'hAB

`define STOSW           8'hAB

`define LODSB           8'hAC

`define LODSB           8'hAC

`define LODSW           8'hAD

`define LODSW           8'hAD

`define SCASB           8'hAE

`define SCASB           8'hAE

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        000 = TEST

        000 = TEST

        001 =

        001 =

        010 = NOT

        010 = NOT

        011 = NEG

        011 = NEG

        100 = MUL

        100 = MUL

        101 =

        101 = IMUL

        110 =

        110 = DIV

        111 =

        111 = IDIV

*/

*/

`define ADDRESS_INACTIVE        20'hFFFFF

`define ADDRESS_INACTIVE        20'hFFFFF

`define DATA_INACTIVE           8'hFF

`define DATA_INACTIVE           8'hFF

`include "cycle_types.v"

`include "cycle_types.v"

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parameter CALL_FIN1 = 8'd211;

parameter CALL_FIN1 = 8'd211;

parameter CALL_FIN2 = 8'd212;

parameter CALL_FIN2 = 8'd212;

parameter CALL_FIN3 = 8'd213;

parameter CALL_FIN3 = 8'd213;

parameter CALL_FIN4 = 8'd214;

parameter CALL_FIN4 = 8'd214;

parameter DIVIDE1 = 8'd215;

parameter DIVIDE1a = 8'd216;

parameter DIVIDE2 = 8'd217;

parameter DIVIDE2a = 8'd218;

parameter DIVIDE3 = 8'd219;

parameter INT = 8'd220;

parameter INT = 8'd220;

parameter INT1 = 8'd221;

parameter INT1 = 8'd221;

parameter INT2 = 8'd222;

parameter INT2 = 8'd222;

parameter INT3 = 8'd223;

parameter INT3 = 8'd223;

parameter INT4 = 8'd224;

parameter INT4 = 8'd224;

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reg [1:0] S43;

reg [1:0] S43;

reg wrregs;

reg wrregs;

reg wrsregs;

reg wrsregs;

wire take_br;

wire take_br;

reg [3:0] shftamt;

reg [3:0] shftamt;

reg ld_div16,ld_div32;          // load divider

reg div_sign;

reg nmi_armed;

reg nmi_armed;

reg rst_nmi;                            // reset the nmi flag

reg rst_nmi;                            // reset the nmi flag

wire pe_nmi;                            // indicates positive edge on nmi signal

wire pe_nmi;                            // indicates positive edge on nmi signal

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`include "REGFILE.v"

`include "REGFILE.v"

`include "CONTROL_LOGIC.v"

`include "CONTROL_LOGIC.v"

`include "which_seg.v"

`include "which_seg.v"

evaluate_branch u4 (ir,cx,zf,cf,sf,vf,pf,take_br);

evaluate_branch u4 (ir,cx,zf,cf,sf,vf,pf,take_br);

`include "ALU.v"

`include "c:\cores\bcxa6\rtl\verilog\eight_bit\ALU.v"

nmi_detector u6 (RESET, CLK, NMI, rst_nmi, pe_nmi);

nmi_detector u6 (RESET, CLK, NMI, rst_nmi, pe_nmi);

always @(posedge CLK)

always @(posedge CLK)

        if (RESET) begin

        if (RESET) begin

                pf <= 1'b0;

                pf <= 1'b0;

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Line 738...

                prefix1 <= 8'h00;

                prefix1 <= 8'h00;

                prefix2 <= 8'h00;

                prefix2 <= 8'h00;

                rst_nmi <= 1'b1;

                rst_nmi <= 1'b1;

                wrregs <= 1'b0;

                wrregs <= 1'b0;

                wrsregs <= 1'b0;

                wrsregs <= 1'b0;

                ld_div16 <= 1'b0;

                ld_div32 <= 1'b0;

                state <= IFETCH;

                state <= IFETCH;

end

end

        else begin

        else begin

                rst_nmi <= 1'b0;

                rst_nmi <= 1'b0;

                wrregs <= 1'b0;

                wrregs <= 1'b0;

                wrsregs <= 1'b0;

                wrsregs <= 1'b0;

                ld_div16 <= 1'b0;

                ld_div32 <= 1'b0;

`include "WRITE_BACK.v"

`include "WRITE_BACK.v"

                case(state)

                case(state)

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`include "OUTB.v"

`include "OUTB.v"

`include "OUTW.v"

`include "OUTW.v"

`include "INSB.v"

`include "INSB.v"

`include "OUTSB.v"

`include "OUTSB.v"

`include "XCHG_MEM.v"

`include "XCHG_MEM.v"

`include "DIVIDE.v"

                        default:

                        default:

                                state <= IFETCH;

                                state <= IFETCH;

                        endcase

                        endcase

end

end

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [rtf8088.v] - Diff between revs 4 and 6