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/* ============================================================================
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// ============================================================================
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2007,2011 Robert Finch
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// (C) 2007,2011,2013 Robert Finch
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robfinch@<remove>sympatico.ca
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// All rights reserved.
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// robfinch@<remove>finitron.ca
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rtfSimpleUart.v
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//
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Basic uart with baud rate generator based on a harmonic
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// rtfSimpleUart.v
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frequency synthesizer.
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// Basic uart with baud rate generator based on a harmonic
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// frequency synthesizer.
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This source code is available for evaluation and validation purposes
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//
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only. This copyright statement and disclaimer must remain present in
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//
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the file.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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NO WARRANTY.
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// notice, this list of conditions and the following disclaimer.
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THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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// * Redistributions in binary form must reproduce the above copyright
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EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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// notice, this list of conditions and the following disclaimer in the
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Work.
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the <organization> nor the
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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// names of its contributors may be used to endorse or promote products
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INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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// derived from this software without specific prior written permission.
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THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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To use:
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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Set the pClkFreq parameter to the frequency of the system
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//
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clock (clk_i). This can be done when the core is instanced.
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// To use:
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//
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1) set the baud rate value in the clock multiplier
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// Set the pClkFreq parameter to the frequency of the system
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registers (CM1,2,3). A default multiplier value may
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// clock (clk_i). This can be done when the core is instanced.
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be specified using the pClkMul parameter, so it
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//
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doesn't have to be programmed at run time. (Note the
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// 1) set the baud rate value in the clock multiplier
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pBaud parameter may also be set, but it doesn't work
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// registers (CM1,2,3). A default multiplier value may
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in all cases due to arithmetic limitations).
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// be specified using the pClkMul parameter, so it
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2) enable communication by activating the rts, and
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// doesn't have to be programmed at run time. (Note the
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dtr signals in the modem control register. These
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// pBaud parameter may also be set, but it doesn't work
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signals are defaulted to be active on reset, so they
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// in all cases due to arithmetic limitations).
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may not need to be set. The pRts and pDtr parameters
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// 2) enable communication by activating the rts, and
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may be used to change the default setting.
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// dtr signals in the modem control register. These
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3) use interrupts or poll the status register to
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// signals are defaulted to be active on reset, so they
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determine when to transmit or receive a byte of data
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// may not need to be set. The pRts and pDtr parameters
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4) read / write the transmit / recieve data buffer
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// may be used to change the default setting.
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for communication.
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// 3) use interrupts or poll the status register to
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// determine when to transmit or receive a byte of data
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Notes:
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// 4) read / write the transmit / recieve data buffer
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This core only supports a single transmission /
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// for communication.
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reception format: 1 start, 8 data, and 1 stop bit (no
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//
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parity).
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// Notes:
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The baud rate generator uses a 24 bit harmonic
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// This core only supports a single transmission /
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frequency synthesizer. Compute the multiplier value
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// reception format: 1 start, 8 data, and 1 stop bit (no
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as if a 32 bit value was needed, then take the upper
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// parity).
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24 bits of the value. (The number of significant bits
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// The baud rate generator uses a 24 bit harmonic
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in the value determine the minimum frequency
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// frequency synthesizer. Compute the multiplier value
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resolution or the precision of the value).
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// as if a 32 bit value was needed, then take the upper
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// 24 bits of the value. (The number of significant bits
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baud rate * 16
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// in the value determine the minimum frequency
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value = -----------------------
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// resolution or the precision of the value).
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(clock frequency / 2^32)
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//
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// baud rate * 16
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eg 38400 * 16
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// value = -----------------------
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value = -----------------------
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// (clock frequency / 2^32)
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(28.63636MHz / 2^32)
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//
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// eg 38400 * 16
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= 92149557.65
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// value = -----------------------
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= 057E1736 (hex)
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// (28.63636MHz / 2^32)
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//
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// = 92149557.65
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taking the upper 24 bits
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// = 057E1736 (hex)
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top 24 = 057E17
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//
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= 359959
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//
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// taking the upper 24 bits
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so the value needed to be programmed into the register
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// top 24 = 057E17
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for 38.4k baud is 57E17 (hex)
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// = 359959
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eg CM0 = 0 (not used)
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//
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CM1 = 17 hex
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// so the value needed to be programmed into the register
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CM2 = 7E hex
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// for 38.4k baud is 57E17 (hex)
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CM3 = 05 hex
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// eg CM0 = 0 (not used)
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// CM1 = 17 hex
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// CM2 = 7E hex
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Register Description
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// CM3 = 05 hex
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//
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reg
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//
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0 read / write (RW)
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// Register Description
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TRB - transmit / receive buffer
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//
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transmit / receive buffer
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// reg
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write - write to transmit buffer
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// 0 read / write (RW)
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read - read from receive buffer
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// TRB - transmit / receive buffer
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// transmit / receive buffer
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1 read only (RO)
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// write - write to transmit buffer
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LS - line status register
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// read - read from receive buffer
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bit 0 = receiver not empty, this bit is set if there is
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//
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any data available in the receiver fifo
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// 1 read only (RO)
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bit 1 = overrun, this bit is set if receiver overrun occurs
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// LS - line status register
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bit 3 = framing error, this bit is set if there was a
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// bit 0 = receiver not empty, this bit is set if there is
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framing error with the current byte in the receiver
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// any data available in the receiver fifo
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buffer.
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// bit 1 = overrun, this bit is set if receiver overrun occurs
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bit 5 = transmitter not full, this bit is set if the transmitter
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// bit 3 = framing error, this bit is set if there was a
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can accept more data
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// framing error with the current byte in the receiver
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bit 6 = transmitter empty, this bit is set if the transmitter is
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// buffer.
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completely empty
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// bit 5 = transmitter not full, this bit is set if the transmitter
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// can accept more data
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2 MS - modem status register (RO)
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// bit 6 = transmitter empty, this bit is set if the transmitter is
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writing to the modem status register clears the change
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// completely empty
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indicators, which should clear a modem status interrupt
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//
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bit 3 = change on dcd signal
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// 2 MS - modem status register (RO)
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bit 4 = cts signal level
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// writing to the modem status register clears the change
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bit 5 = dsr signal level
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// indicators, which should clear a modem status interrupt
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bit 6 = ri signal level
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// bit 3 = change on dcd signal
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bit 7 = dcd signal level
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// bit 4 = cts signal level
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// bit 5 = dsr signal level
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3 IS - interrupt status register (RO)
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// bit 6 = ri signal level
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bit 0-4 = mailbox number
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// bit 7 = dcd signal level
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bit 0,1 = 00
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//
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bit 2-4 = encoded interrupt value
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// 3 IS - interrupt status register (RO)
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bit 5-6 = not used, reserved
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// bit 0-4 = mailbox number
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bit 7 = 1 = interrupt pending, 0 = no interrupt
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// bit 0,1 = 00
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// bit 2-4 = encoded interrupt value
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4 IE - interrupt enable register (RW)
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// bit 5-6 = not used, reserved
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bit 0 = receive interrupt (data present)
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// bit 7 = 1 = interrupt pending, 0 = no interrupt
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bit 1 = transmit interrupt (data empty)
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//
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bit 3 = modem status (dcd) register change
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// 4 IE - interrupt enable register (RW)
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bit 5-7 = unused, reserved
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// bit 0 = receive interrupt (data present)
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// bit 1 = transmit interrupt (data empty)
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5 FF - frame format register (RW)
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// bit 3 = modem status (dcd) register change
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this register doesn't do anything in the simpleUart
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// bit 5-7 = unused, reserved
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but is reserved for compatiblity with the more
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//
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advanced uart
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// 5 FF - frame format register (RW)
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// this register doesn't do anything in the simpleUart
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6 MC - modem control register (RW)
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// but is reserved for compatiblity with the more
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bit 0 = dtr signal level output
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// advanced uart
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bit 1 = rts signal level output
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//
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// 6 MC - modem control register (RW)
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7 - control register
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// bit 0 = dtr signal level output
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bit 0 = hardware flow control,
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// bit 1 = rts signal level output
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when this bit is set, the transmitter output is
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//
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controlled by the cts signal line automatically
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// 7 - control register
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// bit 0 = hardware flow control,
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// when this bit is set, the transmitter output is
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* Clock multiplier steps the 16xbaud clock frequency
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// controlled by the cts signal line automatically
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in increments of 1/2^32 of the clk_i input using a
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//
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harmonic frequency synthesizer
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//
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eg. to get a 9600 baud 16x clock (153.6 kHz) with a
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// * Clock multiplier steps the 16xbaud clock frequency
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27.175 MHz clock input,
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// in increments of 1/2^32 of the clk_i input using a
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value = upper24(9600 * 16 / (27.175MHz / 2^32))
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// harmonic frequency synthesizer
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Higher frequency baud rates will exhibit more jitter
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// eg. to get a 9600 baud 16x clock (153.6 kHz) with a
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on the 16x clock, but this will mostly be masked by the
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// 27.175 MHz clock input,
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16x clock factor.
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// value = upper24(9600 * 16 / (27.175MHz / 2^32))
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// Higher frequency baud rates will exhibit more jitter
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8 CM0 - Clock Multiplier byte 0 (RW)
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// on the 16x clock, but this will mostly be masked by the
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this is the least significant byte
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// 16x clock factor.
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of the clock multiplier value
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//
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this register is not used unless the clock
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// 8 CM0 - Clock Multiplier byte 0 (RW)
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multiplier is set to contain 32 bit values
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// this is the least significant byte
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// of the clock multiplier value
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9 CM1 - Clock Multiplier byte 1 (RW)
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// this register is not used unless the clock
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this is the third most significant byte
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// multiplier is set to contain 32 bit values
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of the clock multiplier value
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//
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this register is not used unless the clock
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// 9 CM1 - Clock Multiplier byte 1 (RW)
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multiplier is set to contain 24 or 32 bit values
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// this is the third most significant byte
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// of the clock multiplier value
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10 CM2 - Clock Multiplier byte 2 (RW)
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// this register is not used unless the clock
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this is the second most significant byte of the clock
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// multiplier is set to contain 24 or 32 bit values
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multiplier value
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//
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// 10 CM2 - Clock Multiplier byte 2 (RW)
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11 CM3 - Clock Multiplier byte 3 (RW)
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// this is the second most significant byte of the clock
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this is the most significant byte of the multiplier value
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// multiplier value
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//
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12 FC - Fifo control register (RW)
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// 11 CM3 - Clock Multiplier byte 3 (RW)
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this register doesnt' do anything in the simpleUart
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// this is the most significant byte of the multiplier value
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but is reserved for compatibility with the more
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//
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advanced uart
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// 12 FC - Fifo control register (RW)
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// this register doesnt' do anything in the simpleUart
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13-14 reserved registers
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// but is reserved for compatibility with the more
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// advanced uart
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15 SPR - scratch pad register (RW)
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//
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// 13-14 reserved registers
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//
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// 15 SPR - scratch pad register (RW)
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|WISHBONE Datasheet
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//
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|WISHBONE SoC Architecture Specification, Revision B.3
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//
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Description: Specifications:
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// |WISHBONE Datasheet
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |WISHBONE SoC Architecture Specification, Revision B.3
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|General Description: simple UART core
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// |
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Description: Specifications:
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|Supported Cycles: SLAVE,READ/WRITE
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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| SLAVE,BLOCK READ/WRITE
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// |General Description: simple UART core
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| SLAVE,RMW
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Supported Cycles: SLAVE,READ/WRITE
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|Data port, size: 8 bit
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// | SLAVE,BLOCK READ/WRITE
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|Data port, granularity: 8 bit
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// | SLAVE,RMW
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|Data port, maximum operand size: 8 bit
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Data transfer ordering: Undefined
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// |Data port, size: 8 bit
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|Data transfer sequencing: Undefined
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// |Data port, granularity: 8 bit
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Data port, maximum operand size: 8 bit
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|Clock frequency constraints: none
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// |Data transfer ordering: Undefined
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Data transfer sequencing: Undefined
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|Supported signal list and Signal Name WISHBONE equiv.
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|cross reference to equivalent ack_o ACK_O
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// |Clock frequency constraints: none
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|WISHBONE signals adr_i[3:0] ADR_I()
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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| clk_i CLK_I
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// |Supported signal list and Signal Name WISHBONE equiv.
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| rst_i RST_I()
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// |cross reference to equivalent ack_o ACK_O
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| dat_i(7:0) DAT_I()
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// |WISHBONE signals adr_i[3:0] ADR_I()
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| dat_o(7:0) DAT_O()
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// | clk_i CLK_I
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| cyc_i CYC_I
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// | rst_i RST_I()
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| stb_i STB_I
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// | dat_i(7:0) DAT_I()
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| we_i WE_I
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// | dat_o(7:0) DAT_O()
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// | cyc_i CYC_I
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// | stb_i STB_I
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|Special requirements:
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// | we_i WE_I
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Special requirements:
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Ref. Spartan3 -4
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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117 LUTs / 87 slices / 133 MHz
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//
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============================================================================ */
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//=============================================================================
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`define UART_TRB 4'd0 // transmit/receive buffer
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`define UART_TRB 4'd0 // transmit/receive buffer
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`define UART_LS 4'd1 // line status register
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`define UART_LS 4'd1 // line status register
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`define UART_MS 4'd2 // modem status register
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`define UART_MS 4'd2 // modem status register
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`define UART_IS 4'd3 // interrupt status register
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`define UART_IS 4'd3 // interrupt status register
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