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/* ============================================================================
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// ============================================================================
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2011 Robert Finch
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// (C) 2011,2013 Robert Finch
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robfinch@<remove>sympatico.ca
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// All rights reserved.
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// robfinch@<remove>finitron.ca
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rtfSimpleUartRx.v
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//
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// rtfSimpleUartRx.v
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This source code is available for evaluation and validation purposes
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//
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only. This copyright statement and disclaimer must remain present in
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// Redistribution and use in source and binary forms, with or without
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the file.
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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NO WARRANTY.
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// * Redistributions in binary form must reproduce the above copyright
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THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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// notice, this list of conditions and the following disclaimer in the
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EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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// documentation and/or other materials provided with the distribution.
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Work.
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// * Neither the name of the <organization> nor the
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// names of its contributors may be used to endorse or promote products
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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// derived from this software without specific prior written permission.
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INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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//
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THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Simple UART receiver core
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//
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Features:
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// Simple UART receiver core
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false start bit detection
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// Features:
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framing error detection
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// false start bit detection
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overrun state detection
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// framing error detection
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resynchronization on every character
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// overrun state detection
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fixed format 1 start - 8 data - 1 stop bits
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// resynchronization on every character
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uses 16x clock rate
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// fixed format 1 start - 8 data - 1 stop bits
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// uses 16x clock rate
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This core may be used as a standalone peripheral
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//
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on a SoC bus if all that is desired is recieve
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// This core may be used as a standalone peripheral
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capability. It requires a 16x baud rate clock.
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// on a SoC bus if all that is desired is recieve
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// capability. It requires a 16x baud rate clock.
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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|WISHBONE Datasheet
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|WISHBONE SoC Architecture Specification, Revision B.3
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// |WISHBONE Datasheet
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// |WISHBONE SoC Architecture Specification, Revision B.3
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|Description: Specifications:
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// |
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Description: Specifications:
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|General Description: simple serial UART receiver
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |General Description: simple serial UART receiver
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|Supported Cycles: SLAVE,READ
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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| SLAVE,BLOCK READ
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// |Supported Cycles: SLAVE,READ
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// | SLAVE,BLOCK READ
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|Data port, size: 8 bit
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Data port, granularity: 8 bit
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// |Data port, size: 8 bit
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|Data port, maximum operand size: 8 bit
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// |Data port, granularity: 8 bit
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|Data transfer ordering: Undefined
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// |Data port, maximum operand size: 8 bit
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|Data transfer sequencing: Undefined
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// |Data transfer ordering: Undefined
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Data transfer sequencing: Undefined
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|Clock frequency constraints: none
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Clock frequency constraints: none
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|Supported signal list and Signal Name WISHBONE equiv.
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|cross reference to equivalent ack_o ACK_O
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// |Supported signal list and Signal Name WISHBONE equiv.
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|WISHBONE signals
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// |cross reference to equivalent ack_o ACK_O
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| clk_i CLK_I
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// |WISHBONE signals
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| rst_i RST_I
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// | clk_i CLK_I
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| dat_o(7:0) DAT_O()
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// | rst_i RST_I
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| cyc_i CYC_I
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// | dat_o(7:0) DAT_O()
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| stb_i STB_I
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// | cyc_i CYC_I
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| we_i WE_I
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// | stb_i STB_I
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// | we_i WE_I
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |
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|Special requirements:
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Special requirements:
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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Ref: Spartan3 -4
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//
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27 LUTs / 24 slices / 170 MHz
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// Ref: Spartan3 -4
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============================================================================ */
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// 27 LUTs / 24 slices / 170 MHz
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//==============================================================================
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`define IDLE 0
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`define IDLE 0
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`define CNT 1
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`define CNT 1
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module rtfSimpleUartRx(
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module rtfSimpleUartRx(
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