| Line 47... |
Line 47... |
|Data port, maximum operand size: 8 bit
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|Data port, maximum operand size: 8 bit
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|Data transfer ordering: Undefined
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|Data transfer ordering: Undefined
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|Data transfer sequencing: Undefined
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|Data transfer sequencing: Undefined
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Clock frequency constraints: none
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|Clock frequency constraints: none
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| Baud Generates by X16 or X8 CLK_I depends on baud8x pin
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|Supported signal list and Signal Name WISHBONE equiv.
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|Supported signal list and Signal Name WISHBONE equiv.
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|cross reference to equivalent ack_o ACK_O
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|cross reference to equivalent ack_o ACK_O
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|WISHBONE signals
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|WISHBONE signals
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| clk_i CLK_I
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| clk_i CLK_I
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| Line 79... |
Line 80... |
input we_i, // write transmitter
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input we_i, // write transmitter
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input [7:0] dat_i, // data in
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input [7:0] dat_i, // data in
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//--------------------
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//--------------------
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input cs_i, // chip select
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input cs_i, // chip select
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input baud16x_ce, // baud rate clock enable
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input baud16x_ce, // baud rate clock enable
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|
input tri0 baud8x, // switches to mode baudX8
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input cts, // clear to send
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input cts, // clear to send
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output txd, // external serial output
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output txd, // external serial output
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output reg empty // buffer is empty
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output reg empty, // buffer is empty
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output reg txc // tx complete flag
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);
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);
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|
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reg [9:0] tx_data; // transmit data working reg (raw)
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reg [9:0] tx_data; // transmit data working reg (raw)
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reg [7:0] fdo; // data output
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reg [7:0] fdo; // data output
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reg [7:0] cnt; // baud clock counter
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reg [7:0] cnt; // baud clock counter
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reg rd;
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reg rd;
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|
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wire isX8;
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buf(isX8, baud8x);
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reg modeX8;
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|
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assign ack_o = cyc_i & stb_i & cs_i;
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assign ack_o = cyc_i & stb_i & cs_i;
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assign txd = tx_data[0];
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assign txd = tx_data[0];
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|
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (ack_o & we_i) fdo <= dat_i;
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if (ack_o & we_i) fdo <= dat_i;
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| Line 103... |
Line 110... |
else begin
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else begin
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if (ack_o & we_i) empty <= 0;
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if (ack_o & we_i) empty <= 0;
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else if (rd) empty <= 1;
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else if (rd) empty <= 1;
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end
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end
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|
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`define CNT_FINISH (8'h9F)
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i) begin
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if (rst_i) begin
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cnt <= 8'h00;
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cnt <= `CNT_FINISH;
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rd <= 0;
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rd <= 0;
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tx_data <= 10'h3FF;
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tx_data <= 10'h3FF;
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txc <= 1'b1;
|
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modeX8 <= 1'b0;
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end
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end
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else begin
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else begin
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|
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rd <= 0;
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rd <= 0;
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|
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if (baud16x_ce) begin
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if (baud16x_ce) begin
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|
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cnt <= cnt + 1;
|
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// Load next data ?
|
// Load next data ?
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if (cnt==8'h9F) begin
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if (cnt==`CNT_FINISH) begin
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cnt <= 0;
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modeX8 <= isX8;
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if (!empty && cts) begin
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if (!empty && cts) begin
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tx_data <= {1'b1,fdo,1'b0};
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tx_data <= {1'b1,fdo,1'b0};
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rd <= 1;
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rd <= 1;
|
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cnt <= modeX8;
|
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txc <= 1'b0;
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end
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end
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else
|
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txc <= 1'b1;
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end
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end
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// Shift the data out. LSB first.
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// Shift the data out. LSB first.
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else if (cnt[3:0]==4'hF)
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else begin
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tx_data <= {1'b1,tx_data[9:1]};
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cnt[7:1] <= cnt[7:1] + cnt[0];
|
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cnt[0] <= ~cnt[0] | (modeX8);
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|
|
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if (cnt[3:0]==4'hF)
|
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tx_data <= {1'b1,tx_data[9:1]};
|
|
end
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end
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end
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end
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end
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|
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endmodule
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endmodule
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No newline at end of file
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