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URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [sparc_ifu_invctl.v] - Diff between revs 105 and 113

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Rev 105 Rev 113
Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
///////////////////////////////////////////////////////////////////////
 
///////////////////////////////////////////////////////////////////////
 
/*
 
/*
 
//  Module Name: sparc_ifu_invctl
 
//  Module Name: sparc_ifu_invctl
 
//  Description:
 
//  Description:
 
//  Control logic for handling invalidations to the icache
 
//  Control logic for handling invalidations to the icache
Line 28... Line 33... 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Global header file includes
 
// Global header file includes
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
/*
 
`include "iop.h"
 
/* ========== Copyright Header Begin ==========================================
 
`include "ifu.h"
 
*
 
 
 
* OpenSPARC T1 Processor File: iop.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
//-*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
//  Description:        Global header file that contain definitions that
 
 
 
//                      are common/shared at the IOP chip level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
 
 
 
 
 
 
// Address Map Defines
 
 
 
// ===================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CMP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                               //`define ENET_ING_CSR     8'h84
 
 
 
                               //`define ENET_EGR_CMD_CSR 8'h85
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2 space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// More IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//Cache Crossbar Width and Field Defines
 
 
 
//======================================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//bits 133:128 are shared by different fields
 
 
 
//for different packet types.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//End cache crossbar defines
 
 
 
 
 
 
 
 
 
 
 
// Number of COS supported by EECU 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// BSC bus sizes
 
 
 
// =============
 
 
 
//
 
 
 
 
 
 
 
// General
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CTags
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// reinstated temporarily
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CoS
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Bank
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Command Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// This is cleaved in between Egress Datapath Ack's
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Datapath
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: EEPU
 
 
 
// Tag is: TLEN, SOF, EOF, QID = 15
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Nack + Tag Info + CTag
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Ingress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Packet Unit Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: PCI
 
 
 
// Tag is: CTAG
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI-X Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI_X Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC array sizes
 
 
 
//================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ECC syndrome bits per memory element
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC Port Definitions
 
 
 
// ====================
 
 
 
//
 
 
 
// Bits 7 to 4 of curr_port_id
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Number of ports of each type
 
 
 
 
 
 
 
 
 
 
 
// Bits needed to represent above
 
 
 
 
 
 
 
 
 
 
 
// How wide the linked list pointers are
 
 
 
// 60b for no payload (2CoS)
 
 
 
// 80b for payload (2CoS)
 
 
 
 
 
 
 
//`define BSC_OBJ_PTR   80
 
 
 
//`define BSC_HD1_HI    69
 
 
 
//`define BSC_HD1_LO    60
 
 
 
//`define BSC_TL1_HI    59
 
 
 
//`define BSC_TL1_LO    50
 
 
 
//`define BSC_CT1_HI    49
 
 
 
//`define BSC_CT1_LO    40
 
 
 
//`define BSC_HD0_HI    29
 
 
 
//`define BSC_HD0_LO    20
 
 
 
//`define BSC_TL0_HI    19
 
 
 
//`define BSC_TL0_LO    10
 
 
 
//`define BSC_CT0_HI     9
 
 
 
//`define BSC_CT0_LO     0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// I2C STATES in DRAMctl
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IOB defines
 
 
 
// ===========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_INT_STAT_WIDTH   32
 
 
 
//`define IOB_INT_STAT_HI      31
 
 
 
//`define IOB_INT_STAT_LO       0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// fixme - double check address mapping
 
 
 
// CREG in `IOB_INT_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CREG in `IOB_MAN_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Address map for TAP access of SPARC ASI
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Bus Width
 
 
 
// ==================
 
 
 
//
 
 
 
//`define IOB_EECU_WIDTH       16  // ethernet egress command
 
 
 
//`define EECU_IOB_WIDTH       16
 
 
 
 
 
 
 
//`define IOB_NRAM_WIDTH       16  // NRAM (RLDRAM previously)
 
 
 
//`define NRAM_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_ENET_ING_WIDTH   32  // ethernet ingress
 
 
 
//`define ENET_ING_IOB_WIDTH    8
 
 
 
 
 
 
 
//`define IOB_ENET_EGR_WIDTH    4  // ethernet egress
 
 
 
//`define ENET_EGR_IOB_WIDTH    4
 
 
 
 
 
 
 
//`define IOB_ENET_MAC_WIDTH    4  // ethernet MAC
 
 
 
//`define ENET_MAC_IOB_WIDTH    4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_BSC_WIDTH         4  // BSC
 
 
 
//`define BSC_IOB_WIDTH         4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_CLSP_WIDTH        4  // clk spine unit
 
 
 
//`define CLSP_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Buf ID Type
 
 
 
// ====================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Interrupt Device ID
 
 
 
// ===================
 
 
 
//
 
 
 
// Caution: DUMMY_DEV_ID has to be 9 bit wide
 
 
 
//          for fields to line up properly in the IOB.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Soft Error related definitions 
 
 
// ==============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CMP clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/IO Interface
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/ENET Interface
 
 
 
// ===================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IO/FCRAM Interface
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Interface
 
 
 
// ==================
 
 
 
// Load/store size encodings
 
 
 
// -------------------------
 
 
 
// Size encoding
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 100 - quad
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI<->SCTAG Interface
 
 
 
// =======================
 
 
 
// Outbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Inbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI->IOB Mondo Header Format
 
 
 
// ============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// JBI->IOB Mondo Bus Width/Cycle
 
 
 
// ==============================
 
 
 
// Cycle  1 Header[15:8]
 
 
 
// Cycle  2 Header[ 7:0]
 
 
 
// Cycle  3 J_AD[127:120]
 
 
 
// Cycle  4 J_AD[119:112]
 
 
 
// .....
 
 
 
// Cycle 18 J_AD[  7:  0]
 
 
 
 
 
 
 
 
 
 
 
/*
 
 
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: ifu.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
//  Module Name: ifu.h
 
 
 
//  Description:
 
 
 
//  All ifu defines
 
 
 
*/
 
 
 
 
 
 
 
//--------------------------------------------
 
 
 
// Icache Values in IFU::ICD/ICV/ICT/FDP/IFQDP
 
 
 
//--------------------------------------------
 
 
 
// Set Values
 
 
 
 
 
 
 
// IC_IDX_HI = log(icache_size/4ways) - 1
 
 
 
 
 
 
 
 
 
 
 
// !!IMPORTANT!! a change to IC_LINE_SZ will mean a change to the code as
 
 
 
//   well.  Unfortunately this has not been properly parametrized.
 
 
 
//   Changing the IC_LINE_SZ param alone is *not* enough.
 
 
 
 
 
 
 
 
 
 
 
// !!IMPORTANT!! a change to IC_TAG_HI will mean a change to the code as
 
 
 
//   well.  Changing the IC_TAG_HI param alone is *not* enough to
 
 
 
//   change the PA range. 
 
 
// highest bit of PA
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Derived Values
 
 
 
// 4095
 
 
 
 
 
 
 
 
 
 
 
// number of entries - 1 = 511
 
 
 
 
 
 
 
 
 
 
 
// 12
 
 
 
 
 
 
 
 
 
 
 
// 28
 
 
 
 
 
 
 
 
 
 
 
// 7
 
 
 
 
 
 
 
 
 
 
 
// tags for all 4 ways + parity
 
 
 
// 116
 
 
 
 
 
 
 
 
 
 
 
// 115
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//----------------------------------------------------------------------
 
 
 
// For thread scheduler in IFU::DTU::SWL
 
 
 
//----------------------------------------------------------------------
 
 
 
// thread states:  (thr_state[4:0])
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// thread configuration register bit fields
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//----------------------------------------------------------------------
 
 
 
// For MIL fsm in IFU::IFQ
 
 
 
//----------------------------------------------------------------------
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//---------------------------------------------------
 
 
 
// Interrupt Block
 
 
 
//---------------------------------------------------
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//-------------------------------------
 
 
 
// IFQ
 
 
 
//-------------------------------------
 
 
 
// valid bit plus ifill
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`ifdef SPARC_L2_64B
 
 
 
 
 
 
 
 
 
 
 
//`else
 
 
 
//`define BANK_ID_HI 8
 
 
 
//`define BANK_ID_LO 7
 
 
 
//`endif
 
 
 
 
 
 
 
//`define CPX_INV_PA_HI  116
 
 
 
//`define CPX_INV_PA_LO  112
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//----------------------------------------
 
 
 
// IFU Traps
 
 
 
//----------------------------------------
 
 
 
// precise
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// disrupting
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
module sparc_ifu_invctl(/*AUTOARG*/
 
module sparc_ifu_invctl(/*AUTOARG*/
 
   // Outputs
 
   // Outputs
 
   so, inv_ifc_inv_pending, ifq_icv_wrindex_bf, ifq_icv_wren_bf,
 
   so, inv_ifc_inv_pending, ifq_icv_wrindex_bf, ifq_icv_wren_bf,
 
   ifq_ict_dec_wrway_bf, ifq_fcl_invreq_bf, ifq_erb_asiway_f,
 
   ifq_ict_dec_wrway_bf, ifq_fcl_invreq_bf, ifq_erb_asiway_f,
Line 1067... Line 55... 
 
 
 
 
 
 
 
 
   input [2:0]  const_cpuid;
 
   input [2:0]  const_cpuid;
 
   input        mbist_icache_write;
 
   input        mbist_icache_write;
 
 
 
 
 
   input [11:5]   lsu_ifu_ld_icache_index;
 
   input [`IC_IDX_HI:5]   lsu_ifu_ld_icache_index;
 
   input                  lsu_ifu_ld_pcxpkt_vld;
 
   input                  lsu_ifu_ld_pcxpkt_vld;
 
   input [1:0]            lsu_ifu_ld_pcxpkt_tid;
 
   input [1:0]            lsu_ifu_ld_pcxpkt_tid;
 
 
 
 
 
   input                  ifc_inv_ifqadv_i2;
 
   input                  ifc_inv_ifqadv_i2;
 
   input                  ifc_inv_asireq_i2;
 
   input                  ifc_inv_asireq_i2;
 
 
 
 
 
   input [11:5]   ifq_icd_index_bf;
 
   input [`IC_IDX_HI:5]   ifq_icd_index_bf;
 
   input [145-1:0] ifd_inv_ifqop_i2;
 
   input [`CPX_WIDTH-1:0] ifd_inv_ifqop_i2;
 
   input [1:0]            ifd_inv_wrway_i2;
 
   input [1:0]            ifd_inv_wrway_i2;
 
 
 
 
 
 
 
 
 
   output                 so;
 
   output                 so;
 
 
 
 
 
   output                 inv_ifc_inv_pending;
 
   output                 inv_ifc_inv_pending;
 
 
 
 
 
   output [11:5]  ifq_icv_wrindex_bf;
 
   output [`IC_IDX_HI:5]  ifq_icv_wrindex_bf;
 
   output [15:0]          ifq_icv_wren_bf;
 
   output [15:0]          ifq_icv_wren_bf;
 
   output [3:0]           ifq_ict_dec_wrway_bf;
 
   output [3:0]           ifq_ict_dec_wrway_bf;
 
   output                 ifq_fcl_invreq_bf;
 
   output                 ifq_fcl_invreq_bf;
 
   output [1:0]           ifq_erb_asiway_f;
 
   output [1:0]           ifq_erb_asiway_f;
 
 
 
 
Line 1156... Line 144... 
               icvidx_sel_inv_i2;
 
               icvidx_sel_inv_i2;
 
 
 
 
 
   wire [15:0] wren_i2;
 
   wire [15:0] wren_i2;
 
 
 
 
 
 
 
 
 
   wire [11:6] inv_addr_i2;
 
   wire [`IC_IDX_HI:6] inv_addr_i2;
 
   wire [11:5] icaddr_i2;
 
   wire [`IC_IDX_HI:5] icaddr_i2;
 
 
 
 
 
   wire                missaddr5_i2;
 
   wire                missaddr5_i2;
 
   wire                missaddr6_i2;
 
   wire                missaddr6_i2;
 
 
 
 
 
 
 
 
 
   wire [3:0]          ldthr,
 
   wire [3:0]          ldthr,
 
                       ldidx_sel_new;
 
                       ldidx_sel_new;
 
 
 
 
 
   wire [11:5] ldinv_addr_i2,
 
   wire [`IC_IDX_HI:5] ldinv_addr_i2,
 
                       ldindex0,
 
                       ldindex0,
 
                       ldindex1,
 
                       ldindex1,
 
                       ldindex2,
 
                       ldindex2,
 
                       ldindex3,
 
                       ldindex3,
 
                       ldindex0_nxt,
 
                       ldindex0_nxt,
Line 1318... Line 306... 
 
 
 
 
   //-----------------------------
 
   //-----------------------------
 
   // Decode CPX Packet
 
   // Decode CPX Packet
 
   //-----------------------------
 
   //-----------------------------
 
   // load
 
   // load
 
   assign ldpkt_i2 = ({ifd_inv_ifqop_i2[144],
 
   assign ldpkt_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
 
                       ifd_inv_ifqop_i2[143:140]} == {1'b1, 4'b0000}) ?
 
                       ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_LDPKT) ?
 
                       1'b1 : 1'b0;
 
                       1'b1 : 1'b0;
 
   assign ldinv_i2 = ldpkt_i2 & ifd_inv_ifqop_i2[133];
 
   assign ldinv_i2 = ldpkt_i2 & ifd_inv_ifqop_i2[`CPX_WYVLD];
 
   assign ldinv_way_i2= ifd_inv_ifqop_i2[132:131];
 
   assign ldinv_way_i2= ifd_inv_ifqop_i2[`CPX_WY_HI:`CPX_WY_LO];
 
 
 
 
 
   // ifill
 
   // ifill
 
   assign imissrtn_i2 = ({ifd_inv_ifqop_i2[144],
 
   assign imissrtn_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
 
                          ifd_inv_ifqop_i2[143:140]} == {1'b1, 4'b0001}) ?
 
                          ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_IFILLPKT) ?
 
                          1'b1 : 1'b0;
 
                          1'b1 : 1'b0;
 
 
 
 
 
   // store ack
 
   // store ack
 
   assign stpkt_i2 = ({ifd_inv_ifqop_i2[144],
 
   assign stpkt_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
 
                       ifd_inv_ifqop_i2[143:140]} == {1'b1, 4'b0100}) ?
 
                       ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_STRPKT) ?
 
                       1'b1 : 1'b0;
 
                       1'b1 : 1'b0;
 
   assign strmack_i2 = ({ifd_inv_ifqop_i2[144],
 
   assign strmack_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
 
                         ifd_inv_ifqop_i2[143:140]} == {1'b1, 4'b0110}) ?
 
                         ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_STRMACK) ?
 
                         1'b1 : 1'b0;
 
                         1'b1 : 1'b0;
 
   assign invall_i2 = stpkt_i2 & ifd_inv_ifqop_i2[124] &
 
   assign invall_i2 = stpkt_i2 & ifd_inv_ifqop_i2[`CPX_IINV] &
 
                      ifc_inv_ifqadv_i2;
 
                      ifc_inv_ifqadv_i2;
 
   assign invpa5_i2 = ifd_inv_ifqop_i2[122];
 
   assign invpa5_i2 = ifd_inv_ifqop_i2[`CPX_INVPA5];
 
 
 
 
 
   // evict 
   // evict 
   assign evpkt_i2 = ({ifd_inv_ifqop_i2[144],
 
   assign evpkt_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
 
                       ifd_inv_ifqop_i2[143:140]} == {1'b1, 4'b0011}) ?
 
                       ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_EVPKT) ?
 
                       1'b1 : 1'b0;
 
                       1'b1 : 1'b0;
 
 
 
 
 
   // get thread id and decode
 
   // get thread id and decode
 
   assign  cpxthrid_i2 = ifd_inv_ifqop_i2[135:134];
 
   assign  cpxthrid_i2 = ifd_inv_ifqop_i2[`CPX_THRFIELD];
 
 
 
 
 
   assign  dcpxthr_i2[0] = ~cpxthrid_i2[1] & ~cpxthrid_i2[0];
 
   assign  dcpxthr_i2[0] = ~cpxthrid_i2[1] & ~cpxthrid_i2[0];
 
   assign  dcpxthr_i2[1] = ~cpxthrid_i2[1] &  cpxthrid_i2[0];
 
   assign  dcpxthr_i2[1] = ~cpxthrid_i2[1] &  cpxthrid_i2[0];
 
   assign  dcpxthr_i2[2] =  cpxthrid_i2[1] & ~cpxthrid_i2[0];
 
   assign  dcpxthr_i2[2] =  cpxthrid_i2[1] & ~cpxthrid_i2[0];
 
   assign  dcpxthr_i2[3] =  cpxthrid_i2[1] &  cpxthrid_i2[0];
 
   assign  dcpxthr_i2[3] =  cpxthrid_i2[1] &  cpxthrid_i2[0];
Line 1366... Line 354... 
   assign  dec_wrway[3] = ifd_inv_wrway_i2[1] & ifd_inv_wrway_i2[0];
 
   assign  dec_wrway[3] = ifd_inv_wrway_i2[1] & ifd_inv_wrway_i2[0];
 
 
 
 
 
   assign  ifq_ict_dec_wrway_bf = dec_wrway;
 
   assign  ifq_ict_dec_wrway_bf = dec_wrway;
 
 
 
 
 
   // way for asi
 
   // way for asi
 
   dff #(2) asiwayf_reg(.din (ifd_inv_wrway_i2),
 
   dff_s #(2) asiwayf_reg(.din (ifd_inv_wrway_i2),
 
                                    .q   (asi_way_f),
 
                                    .q   (asi_way_f),
 
                                    .clk (clk), .se(se), .si(), .so());
 
                                    .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   assign  ifq_erb_asiway_f = asi_way_f;
 
   assign  ifq_erb_asiway_f = asi_way_f;
 
 
 
 
 
 
 
 
 
   // Select which index/way to invalidate
 
   // Select which index/way to invalidate
Line 1390... Line 378... 
   assign w0_way_i2 = pick_wr ? ifd_inv_wrway_i2 :
 
   assign w0_way_i2 = pick_wr ? ifd_inv_wrway_i2 :
 
                                inv0_way_i2;
 
                                inv0_way_i2;
 
   assign w1_way_i2 = pick_wr ? ifd_inv_wrway_i2 :
 
   assign w1_way_i2 = pick_wr ? ifd_inv_wrway_i2 :
 
                                inv1_way_i2;
 
                                inv1_way_i2;
 
 
 
 
 
   dff #(4) wrway_reg(.din ({w0_way_i2, w1_way_i2}),
 
   dff_s #(4) wrway_reg(.din ({w0_way_i2, w1_way_i2}),
 
                      .q   ({w0_way_f, w1_way_f}),
 
                      .q   ({w0_way_f, w1_way_f}),
 
                      .clk (clk), .se(se), .si(), .so());
 
                      .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // determine the way in the ICV we are writing to
 
   // determine the way in the ICV we are writing to
 
//   mux3ds #(2) w0_waymux(.dout  (w0_way_i2),
 
//   mux3ds #(2) w0_waymux(.dout  (w0_way_i2),
 
//                                   .in0   (ifd_inv_wrway_i2[1:0]),
 
//                                   .in0   (ifd_inv_wrway_i2[1:0]),
 
//                                   .in1   (invwd0_way_i2[1:0]),
 
//                                   .in1   (invwd0_way_i2[1:0]),
Line 1446... Line 434... 
                                              ldinv_i2 & ldinv_addr_i2[5] & ldinv_addr_i2[6] |
 
                                              ldinv_i2 & ldinv_addr_i2[5] & ldinv_addr_i2[6] |
 
                                        icv_wrreq_i2 & missaddr5_i2 & missaddr6_i2;
 
                                        icv_wrreq_i2 & missaddr5_i2 & missaddr6_i2;
 
 
 
 
 
   assign wrt_en_wd_bf = ifc_inv_ifqadv_i2 ? wrt_en_wd_i2 :
 
   assign wrt_en_wd_bf = ifc_inv_ifqadv_i2 ? wrt_en_wd_i2 :
 
                                              wrt_en_wd_f;
 
                                              wrt_en_wd_f;
 
   dff #(4) wrten_reg(.din (wrt_en_wd_bf),
 
   dff_s #(4) wrten_reg(.din (wrt_en_wd_bf),
 
                      .q   (wrt_en_wd_f),
 
                      .q   (wrt_en_wd_f),
 
                      .clk (clk), .se(se), .si(), .so());
 
                      .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
 
 
 
 
   // Final Write Enable to ICV
 
   // Final Write Enable to ICV
 
   assign wren_i2[3:0] = (w0_dec_way_i2 & {4{wrt_en_wd_bf[0]}}) |
 
   assign wren_i2[3:0] = (w0_dec_way_i2 & {4{wrt_en_wd_bf[0]}}) |
 
                           {4{invall_i2 & ~invpa5_i2 & ~inv_addr_i2[6]}};
 
                           {4{invall_i2 & ~invpa5_i2 & ~inv_addr_i2[6]}};
Line 1477... Line 465... 
 
 
 
 
//   assign wren_bf = ifc_inv_ifqadv_i2 ? wren_i2 : wren_f;
 
//   assign wren_bf = ifc_inv_ifqadv_i2 ? wren_i2 : wren_f;
 
//   dff #(8) icv_weff(.din  (wren_bf),
 
//   dff #(8) icv_weff(.din  (wren_bf),
 
//                               .q    (wren_f),
 
//                               .q    (wren_f),
 
//                               .clk  (clk),
 
//                               .clk  (clk),
 
//                               .se   (se), .si(), .so());
 
//                               .se   (se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
//   assign ifq_icv_wren_bf[7:0] = wren_bf[7:0] & {8{~icvaddr6_i2}};
 
//   assign ifq_icv_wren_bf[7:0] = wren_bf[7:0] & {8{~icvaddr6_i2}};
 
//   assign ifq_icv_wren_bf[15:8] = wren_bf[7:0] & {8{icvaddr6_i2}};
 
//   assign ifq_icv_wren_bf[15:8] = wren_bf[7:0] & {8{icvaddr6_i2}};
 
 
 
 
 
 
 
 
Line 1489... Line 477... 
   // Invalidates
 
   // Invalidates
 
   //--------------------------
 
   //--------------------------
 
   assign invalidate_i2 = (stpkt_i2 | evpkt_i2 | strmack_i2) &
 
   assign invalidate_i2 = (stpkt_i2 | evpkt_i2 | strmack_i2) &
 
                                              (word0_inv_i2 |
 
                                              (word0_inv_i2 |
 
                             word1_inv_i2 |
 
                             word1_inv_i2 |
 
                                               ifd_inv_ifqop_i2[124]) |  // all ways
 
                                               ifd_inv_ifqop_i2[`CPX_IINV]) |  // all ways
 
                                             ldinv_i2;
 
                                             ldinv_i2;
 
 
 
 
 
   mux2ds #(1) invf_mux(.dout (invreq_i2),
 
   mux2ds #(1) invf_mux(.dout (invreq_i2),
 
                                    .in0  (invalidate_f),
 
                                    .in0  (invalidate_f),
 
                                    .in1  (invalidate_i2),
 
                                    .in1  (invalidate_i2),
 
                                    .sel0  (~ifc_inv_ifqadv_i2),
 
                                    .sel0  (~ifc_inv_ifqadv_i2),
 
                                    .sel1  (ifc_inv_ifqadv_i2));
 
                                    .sel1  (ifc_inv_ifqadv_i2));
 
 
 
 
 
   dff #(1) invf_ff(.din  (invreq_i2),
 
   dff_s #(1) invf_ff(.din  (invreq_i2),
 
                                .q    (invalidate_f),
 
                                .q    (invalidate_f),
 
                                .clk  (clk),
 
                                .clk  (clk),
 
                                .se   (se), .si(), .so());
 
                                .se   (se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // auto invalidate is done during bist
 
   // auto invalidate is done during bist
 
   // no need to qualify bist_write with ifqadv_i2 since bist is done
 
   // no need to qualify bist_write with ifqadv_i2 since bist is done
 
   // before anything else. 
   // before anything else. 
   assign ifq_fcl_invreq_bf = invreq_i2 | mbist_icache_write;
 
   assign ifq_fcl_invreq_bf = invreq_i2 | mbist_icache_write;
Line 1518... Line 506... 
   //---------------------------------
 
   //---------------------------------
 
   // Get the ifill/invalidation index
 
   // Get the ifill/invalidation index
 
   //---------------------------------
 
   //---------------------------------
 
 
 
 
 
   // ifill index
 
   // ifill index
 
   assign icaddr_i2[11:5] = ifq_icd_index_bf[11:5];
 
   assign icaddr_i2[`IC_IDX_HI:5] = ifq_icd_index_bf[`IC_IDX_HI:5];
 
   assign missaddr5_i2 = ifq_icd_index_bf[5];
 
   assign missaddr5_i2 = ifq_icd_index_bf[5];
 
   assign missaddr6_i2 = ifq_icd_index_bf[6];
 
   assign missaddr6_i2 = ifq_icd_index_bf[6];
 
 
 
 
 
   // evict invalidate index
 
   // evict invalidate index
 
   //   assign    inv_addr_i2 = ifqop_i2[117:112];
 
   //   assign    inv_addr_i2 = ifqop_i2[117:112];
 
   assign inv_addr_i2 = ifd_inv_ifqop_i2[117:112];
 
   assign inv_addr_i2 = ifd_inv_ifqop_i2[`CPX_INV_IDX_HI:`CPX_INV_IDX_LO];
 
 
 
 
 
   // index for invalidates caused by a load
 
   // index for invalidates caused by a load
 
   // store dcache index when a load req is made
 
   // store dcache index when a load req is made
 
 
 
 
 
   assign ldthr[0] = ~lsu_ifu_ld_pcxpkt_tid[1] & ~lsu_ifu_ld_pcxpkt_tid[0];
 
   assign ldthr[0] = ~lsu_ifu_ld_pcxpkt_tid[1] & ~lsu_ifu_ld_pcxpkt_tid[0];
Line 1565... Line 553... 
//                                                         .sel  (ldidx_sel_new[3]));
 
//                                                         .sel  (ldidx_sel_new[3]));
 
   assign ldindex3_nxt = ldidx_sel_new[3] ? lsu_ifu_ld_icache_index :
 
   assign ldindex3_nxt = ldidx_sel_new[3] ? lsu_ifu_ld_icache_index :
 
                                            ldindex3;
 
                                            ldindex3;
 
 
 
 
 
 
 
 
 
   dff #((11 - 4))  ldix0_reg(.din (ldindex0_nxt),
 
   dff_s #(`IC_IDX_SZ)  ldix0_reg(.din (ldindex0_nxt),
 
                                            .q   (ldindex0),
 
                                            .q   (ldindex0),
 
                                            .clk (clk), .se(se), .si(), .so());
 
                                            .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff #((11 - 4))  ldix1_reg(.din (ldindex1_nxt),
 
   dff_s #(`IC_IDX_SZ)  ldix1_reg(.din (ldindex1_nxt),
 
                                            .q   (ldindex1),
 
                                            .q   (ldindex1),
 
                                            .clk (clk), .se(se), .si(), .so());
 
                                            .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff #((11 - 4))  ldix2_reg(.din (ldindex2_nxt),
 
   dff_s #(`IC_IDX_SZ)  ldix2_reg(.din (ldindex2_nxt),
 
                                            .q   (ldindex2),
 
                                            .q   (ldindex2),
 
                                            .clk (clk), .se(se), .si(), .so());
 
                                            .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
   dff #((11 - 4))  ldix3_reg(.din (ldindex3_nxt),
 
   dff_s #(`IC_IDX_SZ)  ldix3_reg(.din (ldindex3_nxt),
 
                                            .q   (ldindex3),
 
                                            .q   (ldindex3),
 
                                            .clk (clk), .se(se), .si(), .so());
 
                                            .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
 
 
 
 
   // Pick dcache index corresponding to current thread
 
   // Pick dcache index corresponding to current thread
 
   mux4ds #((11 - 4)) ldinv_mux(.dout (ldinv_addr_i2),
 
   mux4ds #(`IC_IDX_SZ) ldinv_mux(.dout (ldinv_addr_i2),
 
                                                    .in0  (ldindex0),
 
                                                    .in0  (ldindex0),
 
                                                    .in1  (ldindex1),
 
                                                    .in1  (ldindex1),
 
                                                    .in2  (ldindex2),
 
                                                    .in2  (ldindex2),
 
                                                    .in3  (ldindex3),
 
                                                    .in3  (ldindex3),
 
                                                    .sel0 (dcpxthr_i2[0]),
 
                                                    .sel0 (dcpxthr_i2[0]),
Line 1597... Line 585... 
   assign icvidx_sel_ld_i2 = ldinv_i2 & ifc_inv_ifqadv_i2;
 
   assign icvidx_sel_ld_i2 = ldinv_i2 & ifc_inv_ifqadv_i2;
 
   assign icvidx_sel_inv_i2 = ~imissrtn_i2 & ~ldinv_i2 &
 
   assign icvidx_sel_inv_i2 = ~imissrtn_i2 & ~ldinv_i2 &
 
                              ~ifc_inv_asireq_i2 & ifc_inv_ifqadv_i2 &
 
                              ~ifc_inv_asireq_i2 & ifc_inv_ifqadv_i2 &
 
                              ~mbist_icache_write;
 
                              ~mbist_icache_write;
 
 
 
 
 
   mux3ds #((11 - 4)) icv_idx_mux(
 
   mux3ds #(`IC_IDX_SZ) icv_idx_mux(
 
                            .dout  (ifq_icv_wrindex_bf[11:5]),
 
                            .dout  (ifq_icv_wrindex_bf[`IC_IDX_HI:5]),
 
                                              .in0   (icaddr_i2[11:5]),
 
                                              .in0   (icaddr_i2[`IC_IDX_HI:5]),
 
                                              .in1   ({inv_addr_i2[11:6], 1'b0}),
 
                                              .in1   ({inv_addr_i2[`IC_IDX_HI:6], 1'b0}),
 
                                              .in2   (ldinv_addr_i2[11:5]),
 
                                              .in2   (ldinv_addr_i2[`IC_IDX_HI:5]),
 
                                              .sel0  (icvidx_sel_wr_i2),
 
                                              .sel0  (icvidx_sel_wr_i2),
 
                                              .sel1  (icvidx_sel_inv_i2),
 
                                              .sel1  (icvidx_sel_inv_i2),
 
                                              .sel2  (icvidx_sel_ld_i2));
 
                                              .sel2  (icvidx_sel_ld_i2));
 
 
 
 
 
   sink #(145) s0(.in (ifd_inv_ifqop_i2));
 
   sink #(`CPX_WIDTH) s0(.in (ifd_inv_ifqop_i2));
 
 
 
 
 
 
 
 
 
endmodule // sparc_ifu_invctl
 
endmodule // sparc_ifu_invctl
 
 
 
 
 
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