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[/] [s6soc/] [trunk/] [rtl/] [altbusmaster.v] - Diff between revs 8 and 11

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Rev 8 Rev 11
Line 36... Line 36...
//
//
//
//
//
//
`include "builddate.v"
`include "builddate.v"
//
//
`define IMPLEMENT_ONCHIP_RAM
// `define      IMPLEMENT_ONCHIP_RAM
`ifndef VERILATOR
`ifndef VERILATOR
`define FANCY_ICAP_ACCESS
`define FANCY_ICAP_ACCESS
`endif
`endif
`define FLASH_ACCESS
`define FLASH_ACCESS
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
`define INCLUDE_RTC     // About 90 LUTs
`define INCLUDE_RTC     // About 90 LUTs
 
`define WBUBUS
module  altbusmaster(i_clk, i_rst,
module  altbusmaster(i_clk, i_rst,
                // DEPP I/O Control
                // DEPP I/O Control
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
                        i_depp_data, o_depp_data, o_depp_wait,
                        i_depp_data, o_depp_data, o_depp_wait,
                // External UART interface
                // External UART interface
Line 121... Line 122...
        //
        //
        //
        //
        // The BUS master (source): The WB to UART conversion bus
        // The BUS master (source): The WB to UART conversion bus
        //
        //
        //
        //
        wbubus busbdriver(i_clk, i_rx_stb, i_rx_data,
        wire            dep_rx_stb, dep_tx_stb, dep_tx_busy;
 
        wire    [7:0]    dep_rx_data, dep_tx_data;
 
        deppbyte        deppdrive(i_clk,
 
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
 
                        i_depp_data, o_depp_data, o_depp_wait,
 
                dep_rx_stb, dep_rx_data,
 
                dep_tx_stb, dep_tx_data, dep_tx_busy);
 
 
 
        wbubus busbdriver(i_clk,
 
                        // i_rx_stb, i_rx_data,         // UART control
 
                        dep_rx_stb, dep_rx_data,        // DEPP control
                        // The wishbone interface
                        // The wishbone interface
                        wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
                        wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
                                wb_ack, wb_stall, wb_err, wb_idata,
                                wb_ack, wb_stall, wb_err, wb_idata,
                        w_interrupt,
                        w_interrupt,
                        // Provide feedback to the UART
                        // Provide feedback to the DEPP interface
                        o_tx_stb, o_tx_data, i_tx_busy);
                        dep_tx_stb, dep_tx_data, dep_tx_busy);
        assign  o_uart_rts = (~rx_rdy);
//                      // Provide feedback to the UART
 
//                      o_tx_stb, o_tx_data, i_tx_busy
 
        // assign       o_uart_rts = (~rx_rdy);
`else
`else
        //
        //
        //
        //
        // Another BUS master (source): A conversion from DEPP to busmaster
        // Another BUS master (source): A conversion from DEPP to busmaster
        //
        //
Line 237... Line 250...
 
 
        //
        //
        //
        //
        //
        //
        reg             rx_rdy;
        reg             rx_rdy;
        wire    [10:0]   int_vector;
        wire    [11:0]   int_vector;
        assign  int_vector = { gpio_int, pwm_int, keypad_int,
        assign  int_vector = { flash_interrupt, gpio_int, pwm_int, keypad_int,
                                ~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
                                ~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
                                rtc_interrupt, scop_interrupt,
                                rtc_interrupt, scop_interrupt,
                                wb_err, button_int };
                                wb_err, button_int };
 
 
        wire    [31:0]   pic_data;
        wire    [31:0]   pic_data;
        icontrol #(11)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
        icontrol #(12)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
                        wb_data, pic_data, int_vector, w_interrupt);
                        wb_data, pic_data, int_vector, w_interrupt);
 
 
        initial bus_err_addr = 0; // `DATESTAMP;
        initial bus_err_addr = 0; // `DATESTAMP;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (wb_err)
                if (wb_err)
                        bus_err_addr <= wb_addr;
                        bus_err_addr <= wb_addr;
 
 
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
 
        wire    [31:0]   timer_a, timer_b;
        wire    [31:0]   timer_a, timer_b;
 
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
        ziptimer        #(32,20)
        ziptimer        #(32,20)
                zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
                zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
                                tmra_int);
                                tmra_int);
Line 378... Line 391...
 
 
 
 
        //
        //
        //      FLASH MEMORY CONFIGURATION ACCESS
        //      FLASH MEMORY CONFIGURATION ACCESS
        //
        //
        wire    flash_cs_n, flash_sck, flash_mosi;
 
        wbqspiflashp #(24)      flashmem(i_clk,
        wbqspiflashp #(24)      flashmem(i_clk,
                wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
                wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
                        wb_addr[(24-3):0], wb_data,
                        wb_addr[(24-3):0], wb_data,
                flash_ack, flash_stall, flash_data,
                flash_ack, flash_stall, flash_data,
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
                flash_interrupt);
                flash_interrupt);
 
 

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