| Line 41... |
Line 41... |
`define IMPLEMENT_ONCHIP_RAM
|
`define IMPLEMENT_ONCHIP_RAM
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`ifndef VERILATOR
|
`ifndef VERILATOR
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`define FANCY_ICAP_ACCESS
|
`define FANCY_ICAP_ACCESS
|
`endif
|
`endif
|
`define FLASH_ACCESS
|
`define FLASH_ACCESS
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`define CFG_SCOPE
|
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
|
`define INCLUDE_RTC // 2017 slice LUTs w/o, 2108 with (!!!)
|
`define INCLUDE_RTC // About 90 LUTs
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module altbusmaster(i_clk, i_rst,
|
module altbusmaster(i_clk, i_rst,
|
|
// DEPP I/O Control
|
|
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
|
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i_depp_data, o_depp_data, o_depp_wait,
|
|
// External UART interface
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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o_uart_rts,
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o_uart_rts,
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// The SPI Flash lines
|
// The SPI Flash lines
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
|
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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// The board I/O
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// The board I/O
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| Line 56... |
Line 60... |
i_kp_row, o_kp_col,
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i_kp_row, o_kp_col,
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// UART control
|
// UART control
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o_uart_setup,
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o_uart_setup,
|
// GPIO lines
|
// GPIO lines
|
i_gpio, o_gpio);
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i_gpio, o_gpio);
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parameter ZIP_ADDRESS_WIDTH=23, ZA=ZIP_ADDRESS_WIDTH,
|
parameter BUS_ADDRESS_WIDTH=23,
|
CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
|
BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
|
BUS_ADDRESS_WIDTH=23, BAW=23; // 24bits->2,258,23b->2181
|
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input i_clk, i_rst;
|
input i_clk, i_rst;
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// The bus commander, via an external JTAG port
|
// The bus commander, via an external DEPP port
|
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input i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
|
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input wire [7:0] i_depp_data;
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output wire [7:0] o_depp_data;
|
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output wire o_depp_wait;
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// Serial inputs
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input i_rx_stb;
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input i_rx_stb;
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input [7:0] i_rx_data;
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input [7:0] i_rx_data;
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output wire o_tx_stb;
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output reg o_tx_stb;
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output wire [7:0] o_tx_data;
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output reg [7:0] o_tx_data;
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input i_tx_busy;
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input i_tx_busy;
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output wire o_uart_rts;
|
output wire o_uart_rts;
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// SPI flash control
|
// SPI flash control
|
output wire o_qspi_cs_n, o_qspi_sck;
|
output wire o_qspi_cs_n, o_qspi_sck;
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output wire [3:0] o_qspi_dat;
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output wire [3:0] o_qspi_dat;
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| Line 93... |
Line 101... |
//
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//
|
// Master wishbone wires
|
// Master wishbone wires
|
//
|
//
|
//
|
//
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wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
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wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
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wire [31:0] wb_data, wb_idata;
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wire [31:0] wb_data, wb_idata, w_wbu_addr;
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wire [(BAW-1):0] wb_addr;
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wire [(BAW-1):0] wb_addr;
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wire [5:0] io_addr;
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wire [5:0] io_addr;
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assign io_addr = {
|
assign io_addr = {
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wb_addr[22], // Flash
|
wb_addr[22], // Flash
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wb_addr[13], // RAM
|
wb_addr[13], // RAM
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| Line 107... |
Line 115... |
wb_addr[ 8] }; // I/O
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wb_addr[ 8] }; // I/O
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|
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// Wires going to devices
|
// Wires going to devices
|
// And then headed back home
|
// And then headed back home
|
wire w_interrupt;
|
wire w_interrupt;
|
// Oh, and the debug control for the ZIP CPU
|
`ifdef WBUBUS
|
wire zip_dbg_ack, zip_dbg_stall;
|
|
wire [31:0] zip_dbg_data;
|
|
|
|
|
|
//
|
//
|
//
|
//
|
// The BUS master (source): The WB to UART conversion bus
|
// The BUS master (source): The WB to UART conversion bus
|
//
|
//
|
//
|
//
|
wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
|
|
wire [(ZA-1):0] w_zip_addr;
|
|
wire [(BAW-1):0] zip_addr;
|
|
wire [31:0] zip_data;
|
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// and then coming from devices
|
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wire zip_ack, zip_stall, zip_err;
|
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wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
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wire [(BAW-1):0] dwb_addr;
|
|
wire [31:0] dwb_odata;
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|
|
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// wire [31:0] zip_debug;
|
|
wbubus busbdriver(i_clk, i_rx_stb, i_rx_data,
|
wbubus busbdriver(i_clk, i_rx_stb, i_rx_data,
|
// The wishbone interface
|
// The wishbone interface
|
wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
|
wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
|
wb_ack, wb_stall, wb_err, wb_idata,
|
wb_ack, wb_stall, wb_err, wb_idata,
|
w_interrupt,
|
w_interrupt,
|
// Provide feedback to the UART
|
// Provide feedback to the UART
|
o_tx_stb, o_tx_data, i_tx_busy);
|
o_tx_stb, o_tx_data, i_tx_busy);
|
assign o_uart_rts = (~rx_rdy);
|
assign o_uart_rts = (~rx_rdy);
|
|
`else
|
|
//
|
|
//
|
|
// Another BUS master (source): A conversion from DEPP to busmaster
|
|
//
|
|
//
|
|
wbdeppsimple deppdrive(i_clk,
|
|
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
|
|
i_depp_data, o_depp_data, o_depp_wait,
|
|
wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
|
|
wb_ack, wb_stall, wb_err, wb_idata,
|
|
w_interrupt);
|
|
`endif
|
|
|
generate
|
generate
|
if (ZA < BAW)
|
if (BAW < 32)
|
assign wb_addr = { {(BAW-ZA){1'b0}}, w_wbu_addr };
|
assign wb_addr = w_wbu_addr[(BAW-1):0];
|
else
|
else
|
assign wb_addr = w_zip_addr;
|
assign wb_addr = w_wbu_addr;
|
endgenerate
|
endgenerate
|
|
|
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
|
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
|
rtc_sel, none_sel, many_sel;
|
rtc_sel, none_sel, many_sel;
|
wire flash_ack, scop_ack, cfg_ack, mem_ack;
|
wire flash_ack, scop_ack, cfg_ack, mem_ack;
|
wire rtc_ack, rtc_stall;
|
wire rtc_ack, rtc_stall;
|
`ifdef INCLUDE_RTC
|
`ifdef INCLUDE_RTC
|
assign rtc_stall = 1'b0;
|
assign rtc_stall = 1'b0;
|
`endif
|
`endif
|
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
|
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
|
reg io_ack, uart_ack;
|
reg io_ack;
|
|
|
wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
|
wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
|
spio_data, gpio_data, uart_data;
|
spio_data, gpio_data, uart_data;
|
reg [31:0] io_data;
|
reg [31:0] io_data;
|
reg [(BAW-1):0] bus_err_addr;
|
reg [(BAW-1):0] bus_err_addr;
|
|
|
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
|
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
|
||(uart_ack)
|
|
`ifdef INCLUDE_RTC
|
`ifdef INCLUDE_RTC
|
||(rtc_ack)
|
||(rtc_ack)
|
`endif
|
`endif
|
||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
|
||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
|
assign wb_stall = ((io_sel)&&(io_stall))
|
assign wb_stall = ((io_sel)&&(io_stall))
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| Line 184... |
Line 189... |
: ((mem_ack)?mem_data
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: ((mem_ack)?mem_data
|
: ((flash_ack)?flash_data
|
: ((flash_ack)?flash_data
|
: 32'h00))));
|
: 32'h00))));
|
*/
|
*/
|
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
|
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
|
: ((cfg_ack|uart_ack) ? ((cfg_ack)?cfg_data: uart_data)
|
|
: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
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: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
|
: flash_data)); // if (flash_ack)
|
: ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
|
assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
|
assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
|
|
|
// Addresses ...
|
// Addresses ...
|
// 0000 xxxx configuration/control registers
|
// 0000 xxxx configuration/control registers
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
|
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
|
assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
|
assign scop_sel =((wb_cyc)&&(io_addr[5:0]==6'h2));
|
assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
|
assign flctl_sel=((wb_cyc)&&(io_addr[5:0]==6'h3));
|
assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1));
|
assign cfg_sel =((wb_cyc)&&(io_addr[5:1]==5'h2));
|
// zip_sel is not on the bus at this point
|
// zip_sel is not on the bus at this point
|
`ifdef INCLUDE_RTC
|
`ifdef INCLUDE_RTC
|
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
|
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
|
`endif
|
`endif
|
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
|
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
|
assign flash_sel=((wb_cyc)&&(io_addr[5]));
|
assign flash_sel=((wb_cyc)&&(io_addr[5]));
|
|
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
|
/*
|
assign many_sel =((wb_cyc)&&(wb_stb)&&(
|
assign many_sel =((wb_cyc)&&(wb_stb)&&(
|
{3'h0, io_sel}
|
{3'h0, io_sel}
|
+{3'h0, flctl_sel}
|
+{3'h0, flctl_sel}
|
+{3'h0, scop_sel}
|
// +{3'h0, scop_sel}
|
+{3'h0, cfg_sel}
|
+{3'h0, cfg_sel}
|
+{3'h0, rtc_sel}
|
+{3'h0, mem_sel}
|
+{3'h0, mem_sel}
|
+{3'h0, flash_sel} > 1));
|
+{3'h0, flash_sel} > 1));
|
*/
|
// assign many_sel = 1'b0;
|
assign many_sel = 1'b0;
|
|
|
|
wire many_ack;
|
wire many_ack;
|
assign many_ack =((wb_cyc)&&(
|
assign many_ack =((wb_cyc)&&(
|
{3'h0, io_ack}
|
{3'h0, io_ack}
|
+{3'h0, scop_ack}
|
+{3'h0, scop_ack}
|
| Line 236... |
Line 239... |
//
|
//
|
//
|
//
|
reg rx_rdy;
|
reg rx_rdy;
|
wire [10:0] int_vector;
|
wire [10:0] int_vector;
|
assign int_vector = { gpio_int, pwm_int, keypad_int,
|
assign int_vector = { gpio_int, pwm_int, keypad_int,
|
1'b0, rx_rdy, tmrb_int, tmra_int,
|
~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
|
rtc_interrupt, scop_interrupt,
|
rtc_interrupt, scop_interrupt,
|
wb_err, button_int };
|
wb_err, button_int };
|
|
|
wire [31:0] pic_data;
|
wire [31:0] pic_data;
|
icontrol #(11) pic(i_clk, 1'b0,
|
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
|
(wb_cyc)&&(wb_stb)&&(io_sel)
|
|
&&(wb_addr[3:0]==4'h0)&&(wb_we),
|
&&(wb_addr[3:0]==4'h0)&&(wb_we),
|
wb_data, pic_data, int_vector, w_interrupt);
|
wb_data, pic_data, int_vector, w_interrupt);
|
|
|
initial bus_err_addr = `DATESTAMP;
|
initial bus_err_addr = 0; // `DATESTAMP;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wb_err)
|
if (wb_err)
|
bus_err_addr <= wb_addr;
|
bus_err_addr <= wb_addr;
|
|
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
wire [31:0] timer_a, timer_b;
|
wire [31:0] timer_a, timer_b;
|
ziptimer zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
|
ziptimer #(32,20)
|
|
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
wb_we, wb_data, zta_ack, zta_stall, timer_a,
|
wb_we, wb_data, zta_ack, zta_stall, timer_a,
|
tmra_int);
|
tmra_int);
|
ziptimer zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
|
ziptimer #(32,20)
|
|
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
tmrb_int);
|
tmrb_int);
|
|
|
wire [31:0] rtc_data;
|
wire [31:0] rtc_data;
|
| Line 274... |
Line 278... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_rtc_ack <= ((wb_stb)&&(rtc_sel));
|
r_rtc_ack <= ((wb_stb)&&(rtc_sel));
|
assign rtc_ack = r_rtc_ack;
|
assign rtc_ack = r_rtc_ack;
|
|
|
rtclight
|
rtclight
|
#(32'h35afe5) // 80 MHz clock
|
#(23'h35afe5,23,0,0) // 80 MHz clock
|
thetime(i_clk, wb_cyc,
|
thetime(i_clk, wb_cyc,
|
((wb_stb)&&(rtc_sel)), wb_we,
|
((wb_stb)&&(rtc_sel)), wb_we,
|
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
|
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
|
rtc_interrupt, ppd);
|
rtc_interrupt, ppd);
|
`else
|
`else
|
| Line 336... |
Line 340... |
// = 694.4, or about 0x2b6.
|
// = 694.4, or about 0x2b6.
|
// although the CPU might struggle to keep up at this speed without a
|
// although the CPU might struggle to keep up at this speed without a
|
// hardware buffer.
|
// hardware buffer.
|
//
|
//
|
// We'll add the flag for two stop bits.
|
// We'll add the flag for two stop bits.
|
assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
|
// assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
|
|
assign o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
|
|
|
|
initial o_tx_stb = 1'b0;
|
|
initial o_tx_data = 8'h00;
|
|
always @(posedge i_clk)
|
|
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
|
|
begin
|
|
o_tx_data <= wb_data[7:0];
|
|
o_tx_stb <= 1'b1;
|
|
end
|
|
else if ((o_tx_stb)&&(~i_tx_busy))
|
|
o_tx_stb <= 1'b0;
|
|
initial rx_rdy = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (i_rx_stb)
|
|
r_rx_data <= i_rx_data;
|
|
always @(posedge i_clk)
|
|
begin
|
|
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
|
|
rx_rdy <= i_rx_stb;
|
|
else if (i_rx_stb)
|
|
rx_rdy <= (rx_rdy | i_rx_stb);
|
|
end
|
|
assign o_uart_rts = (~rx_rdy);
|
|
assign uart_data = { 23'h0, ~rx_rdy, r_rx_data };
|
|
//
|
|
// uart_ack gets returned as part of io_ack, since that happens when
|
|
// io_sel and wb_stb are defined
|
|
//
|
|
// always @(posedge i_clk)
|
|
// uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
|
|
|
|
|
|
|
//
|
//
|
// FLASH MEMORY CONFIGURATION ACCESS
|
// FLASH MEMORY CONFIGURATION ACCESS
|
//
|
//
|
wire flash_cs_n, flash_sck, flash_mosi;
|
wire flash_cs_n, flash_sck, flash_mosi;
|
wbqspiflashp #(24) flashmem(i_clk,
|
wbqspiflashp #(24) flashmem(i_clk,
|
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_addr[21:0], wb_data,
|
wb_addr[(24-3):0], wb_data,
|
flash_ack, flash_stall, flash_data,
|
flash_ack, flash_stall, flash_data,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
flash_interrupt);
|
flash_interrupt);
|
|
|
//
|
//
|
| Line 375... |
Line 409... |
|
|
|
|
//
|
//
|
// ON-CHIP RAM MEMORY ACCESS
|
// ON-CHIP RAM MEMORY ACCESS
|
//
|
//
|
|
`ifdef IMPLEMENT_ONCHIP_RAM
|
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
|
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
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`else
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assign mem_data = 32'h00;
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assign mem_stall = 1'b0;
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reg r_mem_ack;
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|
always @(posedge i_clk)
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|
r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
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assign mem_ack = r_mem_ack;
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|
`endif
|
|
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//
|
//
|
//
|
//
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// WISHBONE SCOPE
|
// WISHBONE SCOPE
|
//
|
//
|
//
|
//
|
//
|
//
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//
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//
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wire [31:0] scop_cfg_data;
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wire [31:0] scop_cfg_data;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
`ifdef CFG_SCOPE
|
`ifdef DBG_SCOPE
|
wire scop_cfg_trigger;
|
wire scop_cfg_trigger;
|
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
|
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
|
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
|
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
scop_cfg_interrupt);
|
scop_cfg_interrupt);
|
|
`else
|
|
reg r_scop_cfg_ack;
|
|
always @(posedge i_clk)
|
|
r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
|
|
assign scop_cfg_ack = r_scop_cfg_ack;
|
|
assign scop_cfg_data = 32'h000;
|
|
assign scop_cfg_stall= 1'b0;
|
`endif
|
`endif
|
|
|
assign scop_interrupt = scop_cfg_interrupt;
|
assign scop_interrupt = scop_cfg_interrupt;
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assign scop_ack = scop_cfg_ack;
|
assign scop_ack = scop_cfg_ack;
|
assign scop_stall = scop_cfg_stall;
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assign scop_stall = scop_cfg_stall;
|
assign scop_data = scop_cfg_data;
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assign scop_data = scop_cfg_data;
|
|
|
endmodule
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endmodule
|
|
|
// 0x8684 interrupts ...???
|
|
|
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No newline at end of file
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No newline at end of file
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