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////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    busmaster.v
// Filename:    busmaster.v
//
//
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
//
//
// Purpose:     
// Purpose:     
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
//
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
// You should have received a copy of the GNU General Public License along
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
// <http://www.gnu.org/licenses/> for a copy.
//
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
//
//
//
//
`include "builddate.v"
`include "builddate.v"
//
//
`define INCLUDE_ZIPPY
`define INCLUDE_ZIPPY
`define IMPLEMENT_ONCHIP_RAM    // 2804 w/o after synthesis
`define IMPLEMENT_ONCHIP_RAM    // 2804 w/o after synthesis
`ifndef VERILATOR
`ifndef VERILATOR
`define FANCY_ICAP_ACCESS
`define FANCY_ICAP_ACCESS
`endif
`endif
`define FLASH_ACCESS
`define FLASH_ACCESS
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
// `define      INCLUDE_RTC     // About 90 LUTs
// `define      INCLUDE_RTC     // About 90 LUTs
module  busmaster(i_clk, i_rst,
module  busmaster(i_clk, i_rst,
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
                        o_uart_rts,
                        o_uart_cts,
                // The SPI Flash lines
                // The SPI Flash lines
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
                // The board I/O
                // The board I/O
                i_btn, o_led, o_pwm, o_pwm_aux,
                i_btn, o_led, o_pwm, o_pwm_aux,
                // Keypad connections
                // Keypad connections
                i_kp_row, o_kp_col,
                i_kp_row, o_kp_col,
                // UART control
                // UART control
                o_uart_setup,
                o_uart_setup,
                // GPIO lines
                // GPIO lines
                i_gpio, o_gpio);
                i_gpio, o_gpio);
        parameter       BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
        parameter       BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
                        CMOD_ZIPCPU_RESET_ADDRESS=23'h480000,
                        CMOD_ZIPCPU_RESET_ADDRESS=23'h480000,
                        ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
                        ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
        input                   i_clk, i_rst;
        input                   i_clk, i_rst;
        input                   i_rx_stb;
        input                   i_rx_stb;
        input           [7:0]    i_rx_data;
        input           [7:0]    i_rx_data;
        output  reg             o_tx_stb;
        output  reg             o_tx_stb;
        output  reg     [7:0]    o_tx_data;
        output  reg     [7:0]    o_tx_data;
        input                   i_tx_busy;
        input                   i_tx_busy;
        output  wire            o_uart_rts;
        output  wire            o_uart_cts;
        // SPI flash control
        // SPI flash control
        output  wire            o_qspi_cs_n, o_qspi_sck;
        output  wire            o_qspi_cs_n, o_qspi_sck;
        output  wire    [3:0]    o_qspi_dat;
        output  wire    [3:0]    o_qspi_dat;
        input           [3:0]    i_qspi_dat;
        input           [3:0]    i_qspi_dat;
        output  wire    [1:0]    o_qspi_mod;
        output  wire    [1:0]    o_qspi_mod;
        // Board I/O
        // Board I/O
        input           [1:0]    i_btn;
        input           [1:0]    i_btn;
        output  wire    [3:0]    o_led;
        output  wire    [3:0]    o_led;
        output  wire            o_pwm;
        output  wire            o_pwm;
        output  wire    [1:0]    o_pwm_aux;
        output  wire    [1:0]    o_pwm_aux;
        // Keypad
        // Keypad
        input           [3:0]    i_kp_row;
        input           [3:0]    i_kp_row;
        output  wire    [3:0]    o_kp_col;
        output  wire    [3:0]    o_kp_col;
        // UART control
        // UART control
        output  wire    [29:0]   o_uart_setup;
        output  wire    [29:0]   o_uart_setup;
        // GPIO liines
        // GPIO liines
        input           [15:0]   i_gpio;
        input           [15:0]   i_gpio;
        output  wire    [15:0]   o_gpio;
        output  wire    [15:0]   o_gpio;
 
 
 
 
        //
        //
        //
        //
        // Master wishbone wires
        // Master wishbone wires
        //
        //
        //
        //
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
        wire    [31:0]   wb_data, wb_idata;
        wire    [31:0]   wb_data, wb_idata;
        wire    [(BAW-1):0]      wb_addr;
        wire    [(BAW-1):0]      wb_addr;
        wire    [5:0]            io_addr;
        wire    [5:0]            io_addr;
        assign  io_addr = {
        assign  io_addr = {
                        wb_addr[22],    // Flash
                        wb_addr[22],    // Flash
                        wb_addr[13],    // RAM
                        wb_addr[13],    // RAM
                        wb_addr[11],    // RTC
                        wb_addr[11],    // RTC
                        wb_addr[10],    // CFG
                        wb_addr[10],    // CFG
                        wb_addr[ 9],    // SCOPE
                        wb_addr[ 9],    // SCOPE
                        wb_addr[ 8] };  // I/O
                        wb_addr[ 8] };  // I/O
 
 
        // Wires going to devices
        // Wires going to devices
        // And then headed back home
        // And then headed back home
        wire    w_interrupt;
        wire    w_interrupt;
        // Oh, and the debug control for the ZIP CPU
        // Oh, and the debug control for the ZIP CPU
        wire            zip_dbg_ack, zip_dbg_stall;
        wire            zip_dbg_ack, zip_dbg_stall;
        wire    [31:0]   zip_dbg_data;
        wire    [31:0]   zip_dbg_data;
 
 
 
 
        //
        //
        //
        //
        // The BUS master (source): The ZipCPU
        // The BUS master (source): The ZipCPU
        //
        //
        //
        //
        wire            zip_cyc, zip_stb, zip_we, zip_cpu_int;
        wire            zip_cyc, zip_stb, zip_we, zip_cpu_int;
        wire    [(ZA-1):0]       w_zip_addr;
        wire    [(ZA-1):0]       w_zip_addr;
        wire    [(BAW-1):0]      zip_addr;
        wire    [(BAW-1):0]      zip_addr;
        wire    [31:0]           zip_data;
        wire    [31:0]           zip_data;
        // and then coming from devices
        // and then coming from devices
        wire            zip_ack, zip_stall, zip_err;
        wire            zip_ack, zip_stall, zip_err;
        wire    dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
        wire    dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
        wire    [(BAW-1):0]      dwb_addr;
        wire    [(BAW-1):0]      dwb_addr;
        wire    [31:0]           dwb_odata;
        wire    [31:0]           dwb_odata;
 
 
        // wire [31:0]  zip_debug;
        // wire [31:0]  zip_debug;
//
//
// We'll define our RESET_ADDRESS to be halfway through our flash memory.
// We'll define our RESET_ADDRESS to be halfway through our flash memory.
//      `define CMOD_ZIPCPU_RESET_ADDRESS       23'h600000
//      `define CMOD_ZIPCPU_RESET_ADDRESS       23'h600000
//
//
// Ahm, No.  We can actually do much better than that.  Our toplevel *.bit file
// Ahm, No.  We can actually do much better than that.  Our toplevel *.bit file
// only takes up only 335kB.  Let's give it some room to grow to 1024 kB.  Then
// only takes up only 335kB.  Let's give it some room to grow to 1024 kB.  Then
// 23 can start our ROM at 23'h400100
// 23 can start our ROM at 23'h400100
//
//
// Not so fast.  In hindsight, we really want to be  able to adjust the load and
// Not so fast.  In hindsight, we really want to be  able to adjust the load and
// the program separately.  So, instead, let's place our RESET address at the
// the program separately.  So, instead, let's place our RESET address at the
// second flash erase block.  That way, we can change our program code found
// second flash erase block.  That way, we can change our program code found
// in the flash without needing to change our FPGA load and vice versa.
// in the flash without needing to change our FPGA load and vice versa.
//
//
// 23'h404000
// 23'h404000
        zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
        zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
                thecpu(i_clk, 1'b0,
                thecpu(i_clk, 1'b0,
                        // Zippys wishbone interface
                        // Zippys wishbone interface
                        wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data,
                        wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data,
                                wb_ack, wb_stall, wb_idata, wb_err,
                                wb_ack, wb_stall, wb_idata, wb_err,
                        w_interrupt, zip_cpu_int,
                        w_interrupt, zip_cpu_int,
                        // Debug wishbone interface
                        // Debug wishbone interface
                        1'b0, 1'b0,1'b0, 1'b0, 32'h00,
                        1'b0, 1'b0,1'b0, 1'b0, 32'h00,
                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data);
                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data);
        generate
        generate
        if (ZA < BAW)
        if (ZA < BAW)
                assign  wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
                assign  wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
        else
        else
                assign  wb_addr = w_zip_addr;
                assign  wb_addr = w_zip_addr;
        endgenerate
        endgenerate
 
 
        wire    io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
        wire    io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
                        rtc_sel, none_sel, many_sel;
                        rtc_sel, none_sel, many_sel;
        wire    flash_ack, scop_ack, cfg_ack, mem_ack;
        wire    flash_ack, scop_ack, cfg_ack, mem_ack;
        wire    rtc_ack, rtc_stall;
        wire    rtc_ack, rtc_stall;
`ifdef  INCLUDE_RTC
`ifdef  INCLUDE_RTC
        assign  rtc_stall = 1'b0;
        assign  rtc_stall = 1'b0;
`endif
`endif
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
        reg     io_ack;
        reg     io_ack;
 
 
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
                        spio_data, gpio_data, uart_data;
                        spio_data, gpio_data, uart_data;
        reg     [31:0]   io_data;
        reg     [31:0]   io_data;
        reg     [(BAW-1):0]      bus_err_addr;
        reg     [(BAW-1):0]      bus_err_addr;
 
 
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
`ifdef  INCLUDE_RTC
`ifdef  INCLUDE_RTC
                                ||(rtc_ack)
                                ||(rtc_ack)
`endif
`endif
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
        assign  wb_stall = ((io_sel)&&(io_stall))
        assign  wb_stall = ((io_sel)&&(io_stall))
                        ||((scop_sel)&&(scop_stall))
                        ||((scop_sel)&&(scop_stall))
                        ||((cfg_sel)&&(cfg_stall))
                        ||((cfg_sel)&&(cfg_stall))
                        ||((mem_sel)&&(mem_stall))
                        ||((mem_sel)&&(mem_stall))
`ifdef  INCLUDE_RTC
`ifdef  INCLUDE_RTC
                        ||((rtc_sel)&&(rtc_stall))
                        ||((rtc_sel)&&(rtc_stall))
`endif
`endif
                        ||((flash_sel||flctl_sel)&&(flash_stall));
                        ||((flash_sel||flctl_sel)&&(flash_stall));
                        // (none_sel)&&(1'b0)
                        // (none_sel)&&(1'b0)
 
 
        /*
        /*
        assign  wb_idata = (io_ack)?io_data
        assign  wb_idata = (io_ack)?io_data
                        : ((scop_ack)?scop_data
                        : ((scop_ack)?scop_data
                        : ((cfg_ack)?cfg_data
                        : ((cfg_ack)?cfg_data
                        : ((mem_ack)?mem_data
                        : ((mem_ack)?mem_data
                        : ((flash_ack)?flash_data
                        : ((flash_ack)?flash_data
                        : 32'h00))));
                        : 32'h00))));
        */
        */
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
                        : ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
                        : ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
                        : ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
                        : ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
 
 
        // Addresses ...
        // Addresses ...
        //      0000 xxxx       configuration/control registers
        //      0000 xxxx       configuration/control registers
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
        assign  io_sel   =((wb_cyc)&&(io_addr[5:0]==6'h1));
        assign  io_sel   =((wb_cyc)&&(io_addr[5:0]==6'h1));
        assign  flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
        assign  flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
        assign  scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
        assign  scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
        assign  cfg_sel  =((wb_cyc)&&(io_addr[5:2]==4'h1));
        assign  cfg_sel  =((wb_cyc)&&(io_addr[5:2]==4'h1));
        // zip_sel is not on the bus at this point
        // zip_sel is not on the bus at this point
`ifdef  INCLUDE_RTC
`ifdef  INCLUDE_RTC
        assign  rtc_sel  =((wb_cyc)&&(io_addr[5:3]==3'h1));
        assign  rtc_sel  =((wb_cyc)&&(io_addr[5:3]==3'h1));
`endif
`endif
        assign  mem_sel  =((wb_cyc)&&(io_addr[5:4]==2'h1));
        assign  mem_sel  =((wb_cyc)&&(io_addr[5:4]==2'h1));
        assign  flash_sel=((wb_cyc)&&(io_addr[5]));
        assign  flash_sel=((wb_cyc)&&(io_addr[5]));
 
 
        assign  none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
        assign  none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
        /*
        /*
        assign  many_sel =((wb_cyc)&&(wb_stb)&&(
        assign  many_sel =((wb_cyc)&&(wb_stb)&&(
                         {3'h0, io_sel}
                         {3'h0, io_sel}
                        +{3'h0, flctl_sel}
                        +{3'h0, flctl_sel}
                        +{3'h0, scop_sel}
                        +{3'h0, scop_sel}
                        +{3'h0, cfg_sel}
                        +{3'h0, cfg_sel}
                        +{3'h0, rtc_sel}
                        +{3'h0, rtc_sel}
                        +{3'h0, mem_sel}
                        +{3'h0, mem_sel}
                        +{3'h0, flash_sel} > 1));
                        +{3'h0, flash_sel} > 1));
        */
        */
        assign  many_sel = 1'b0;
        assign  many_sel = 1'b0;
 
 
        wire    many_ack;
        wire    many_ack;
        assign  many_ack =((wb_cyc)&&(
        assign  many_ack =((wb_cyc)&&(
                         {3'h0, io_ack}
                         {3'h0, io_ack}
                        +{3'h0, scop_ack}
                        +{3'h0, scop_ack}
                        +{3'h0, cfg_ack}
                        +{3'h0, cfg_ack}
`ifdef  INCLUDE_RTC
`ifdef  INCLUDE_RTC
                        +{3'h0, rtc_ack}
                        +{3'h0, rtc_ack}
`endif
`endif
                        +{3'h0, mem_ack}
                        +{3'h0, mem_ack}
                        +{3'h0, flash_ack} > 1));
                        +{3'h0, flash_ack} > 1));
 
 
        wire            flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
        wire            flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
                        rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
                        rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
 
 
 
 
        //
        //
        //
        //
        //
        //
        reg             rx_rdy;
        reg             rx_rdy;
        wire    [10:0]   int_vector;
        wire    [10:0]   int_vector;
        assign  int_vector = { gpio_int, pwm_int, keypad_int,
        assign  int_vector = { gpio_int, pwm_int, keypad_int,
                                ~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
                                ~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
                                rtc_interrupt, scop_interrupt,
                                rtc_interrupt, scop_interrupt,
                                wb_err, button_int };
                                wb_err, button_int };
 
 
        wire    [31:0]   pic_data;
        wire    [31:0]   pic_data;
        icontrol #(11)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
        icontrol #(11)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
                        wb_data, pic_data, int_vector, w_interrupt);
                        wb_data, pic_data, int_vector, w_interrupt);
 
 
        initial bus_err_addr = 0; // `DATESTAMP;
        initial bus_err_addr = 0; // `DATESTAMP;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (wb_err)
                if (wb_err)
                        bus_err_addr <= wb_addr;
                        bus_err_addr <= wb_addr;
 
 
        wire    [31:0]   timer_a, timer_b;
        wire    [31:0]   timer_a, timer_b;
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
        ziptimer        #(32,31)
        ziptimer        #(32,31)
                zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
                zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
                                tmra_int);
                                tmra_int);
        ziptimer        #(32,31)
        ziptimer        #(32,31)
                zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
                zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
                                tmrb_int);
                                tmrb_int);
 
 
        wire    [31:0]   rtc_data;
        wire    [31:0]   rtc_data;
`ifdef  INCLUDE_RTC
`ifdef  INCLUDE_RTC
        wire    rtcd_ack, rtcd_stall, ppd;
        wire    rtcd_ack, rtcd_stall, ppd;
        // rtcdate      thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
        // rtcdate      thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
                        // wb_data, rtcd_ack, rtcd_stall, date_data);
                        // wb_data, rtcd_ack, rtcd_stall, date_data);
        reg     r_rtc_ack;
        reg     r_rtc_ack;
        initial r_rtc_ack = 1'b0;
        initial r_rtc_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_rtc_ack <= ((wb_stb)&&(rtc_sel));
                r_rtc_ack <= ((wb_stb)&&(rtc_sel));
        assign  rtc_ack = r_rtc_ack;
        assign  rtc_ack = r_rtc_ack;
 
 
        rtclight
        rtclight
                #(23'h35afe5,23,0,0)      // 80 MHz clock
                #(23'h35afe5,23,0,0)      // 80 MHz clock
                thetime(i_clk, wb_cyc,
                thetime(i_clk, wb_cyc,
                        ((wb_stb)&&(rtc_sel)), wb_we,
                        ((wb_stb)&&(rtc_sel)), wb_we,
                        { 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
                        { 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
                        rtc_interrupt, ppd);
                        rtc_interrupt, ppd);
`else
`else
        assign  rtc_interrupt = 1'b0;
        assign  rtc_interrupt = 1'b0;
        assign  rtc_data = 32'h00;
        assign  rtc_data = 32'h00;
        assign  rtc_ack  = 1'b0;
        assign  rtc_ack  = 1'b0;
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                case(wb_addr[3:0])
                case(wb_addr[3:0])
                        4'h0: io_data <= pic_data;
                        4'h0: io_data <= pic_data;
                        4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
                        4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
                        4'h2: io_data <= timer_a;
                        4'h2: io_data <= timer_a;
                        4'h3: io_data <= timer_b;
                        4'h3: io_data <= timer_b;
                        4'h4: io_data <= pwm_data;
                        4'h4: io_data <= pwm_data;
                        4'h5: io_data <= spio_data;
                        4'h5: io_data <= spio_data;
                        4'h6: io_data <= gpio_data;
                        4'h6: io_data <= gpio_data;
                        4'h7: io_data <= uart_data;
                        4'h7: io_data <= uart_data;
                        default: io_data <= `DATESTAMP;
                        default: io_data <= `DATESTAMP;
                        // 4'h8: io_data <= `DATESTAMP;
                        // 4'h8: io_data <= `DATESTAMP;
                endcase
                endcase
        always @(posedge i_clk)
        always @(posedge i_clk)
                io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
                io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
        assign  io_stall = 1'b0;
        assign  io_stall = 1'b0;
 
 
        wire    pwm_ack, pwm_stall;
        wire    pwm_ack, pwm_stall;
        wbpwmaudio      theaudio(i_clk, wb_cyc,
        wbpwmaudio      #(14'd10000,2,0,14)
                                ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)), wb_we,
                theaudio(i_clk, wb_cyc,
                                1'b0, wb_data,
                                ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
                                pwm_ack, pwm_stall, pwm_data, o_pwm, o_pwm_aux,
                                        wb_we, 1'b0, wb_data,
 
                                pwm_ack, pwm_stall, pwm_data, o_pwm,
 
                                        o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
                                pwm_int);
                                pwm_int);
 
 
        //
        //
        // Special Purpose I/O: Keypad, button, LED status and control
        // Special Purpose I/O: Keypad, button, LED status and control
        //
        //
        spio    thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
        spio    thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
                        wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
                        wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
                        keypad_int, button_int);
                        keypad_int, button_int);
 
 
        //
        //
        // General purpose (sort of) I/O:  (Bottom two bits robbed in each
        // General purpose (sort of) I/O:  (Bottom two bits robbed in each
        // direction for an I2C link at the toplevel.v design)
        // direction for an I2C link at the toplevel.v design)
        //
        //
        wbgpio  #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
        wbgpio  #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
                        (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
                        (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
                        wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
                        wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
 
 
        //
        //
        //
        //
        //      Rudimentary serial port control
        //      Rudimentary serial port control
        //
        //
        reg     [7:0]    r_rx_data;
        reg     [7:0]    r_rx_data;
        // Baud rate is set by clock rate / baud rate.
        // Baud rate is set by clock rate / baud rate.
        // Thus, 80MHz / 115200MBau
        // Thus, 80MHz / 115200MBau
        //      = 694.4, or about 0x2b6. 
        //      = 694.4, or about 0x2b6. 
        // although the CPU might struggle to keep up at this speed without a
        // although the CPU might struggle to keep up at this speed without a
        // hardware buffer.
        // hardware buffer.
        //
        //
        // We'll add the flag for two stop bits.
        // We'll add the flag for two stop bits.
        // assign       o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
        // assign       o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
        assign  o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
        assign  o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
 
 
        initial o_tx_stb = 1'b0;
        initial o_tx_stb = 1'b0;
        initial o_tx_data = 8'h00;
        initial o_tx_data = 8'h00;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
                if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
                begin
                begin
                        o_tx_data <= wb_data[7:0];
                        o_tx_data <= wb_data[7:0];
                        o_tx_stb <= 1'b1;
                        o_tx_stb <= 1'b1;
                end
                end
                else if ((o_tx_stb)&&(~i_tx_busy))
                else if ((o_tx_stb)&&(~i_tx_busy))
                        o_tx_stb <= 1'b0;
                        o_tx_stb <= 1'b0;
        initial rx_rdy = 1'b0;
        initial rx_rdy = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rx_stb)
                if (i_rx_stb)
                        r_rx_data <= i_rx_data;
                        r_rx_data <= i_rx_data;
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
                if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
                        rx_rdy <= i_rx_stb;
                        rx_rdy <= i_rx_stb;
                else if (i_rx_stb)
                else if (i_rx_stb)
                        rx_rdy <= (rx_rdy | i_rx_stb);
                        rx_rdy <= (rx_rdy | i_rx_stb);
        end
        end
        assign  o_uart_rts = (~rx_rdy);
        assign  o_uart_cts = (~rx_rdy);
        assign  uart_data = { 23'h0, ~rx_rdy, r_rx_data };
        assign  uart_data = { 23'h0, ~rx_rdy, r_rx_data };
        //
        //
        // uart_ack gets returned as part of io_ack, since that happens when
        // uart_ack gets returned as part of io_ack, since that happens when
        // io_sel and wb_stb are defined
        // io_sel and wb_stb are defined
        //
        //
        // always @(posedge i_clk)
        // always @(posedge i_clk)
                // uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
                // uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
 
 
 
 
 
 
        //
        //
        //      FLASH MEMORY CONFIGURATION ACCESS
        //      FLASH MEMORY CONFIGURATION ACCESS
        //
        //
        wbqspiflash #(24)       flashmem(i_clk,
        wbqspiflash #(24)       flashmem(i_clk,
                wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
                wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
                        wb_addr[(24-3):0], wb_data,
                        wb_addr[(24-3):0], wb_data,
                flash_ack, flash_stall, flash_data,
                flash_ack, flash_stall, flash_data,
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
                flash_interrupt);
                flash_interrupt);
 
 
        //
        //
        //      MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
        //      MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
        //
        //
        wire    [31:0]   cfg_scope;
        wire    [31:0]   cfg_scope;
`ifdef  FANCY_ICAP_ACCESS
`ifdef  FANCY_ICAP_ACCESS
        wbicape6        fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
        wbicape6        fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
                                wb_addr[5:0], wb_data,
                                wb_addr[5:0], wb_data,
                                cfg_ack, cfg_stall, cfg_data,
                                cfg_ack, cfg_stall, cfg_data,
                                cfg_scope);
                                cfg_scope);
`else
`else
        reg     r_cfg_ack;
        reg     r_cfg_ack;
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
                r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
        assign  cfg_ack   = r_cfg_ack;
        assign  cfg_ack   = r_cfg_ack;
        assign  cfg_stall = 1'b0;
        assign  cfg_stall = 1'b0;
        assign  cfg_data  = 32'h00;
        assign  cfg_data  = 32'h00;
        assign  cfg_scope = 32'h00;
        assign  cfg_scope = 32'h00;
`endif
`endif
 
 
 
 
        //
        //
        //      ON-CHIP RAM MEMORY ACCESS
        //      ON-CHIP RAM MEMORY ACCESS
        //
        //
`ifdef  IMPLEMENT_ONCHIP_RAM
`ifdef  IMPLEMENT_ONCHIP_RAM
        memdev  #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
        memdev  #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
                        wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
                        wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
`else
`else
        assign  mem_data = 32'h00;
        assign  mem_data = 32'h00;
        assign  mem_stall = 1'b0;
        assign  mem_stall = 1'b0;
        reg     r_mem_ack;
        reg     r_mem_ack;
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
                r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
        assign  mem_ack = r_mem_ack;
        assign  mem_ack = r_mem_ack;
`endif
`endif
 
 
        //
        //
        //
        //
        //      WISHBONE SCOPE
        //      WISHBONE SCOPE
        //
        //
        //
        //
        //
        //
        //
        //
        wire    [31:0]   scop_cfg_data;
        wire    [31:0]   scop_cfg_data;
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
`ifdef  DBG_SCOPE
`ifdef  DBG_SCOPE
        wire            scop_cfg_trigger;
        wire            scop_cfg_trigger;
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
        wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
        wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
                // Wishbone interface
                // Wishbone interface
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
                                wb_we, wb_addr[0], wb_data,
                                wb_we, wb_addr[0], wb_data,
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
                scop_cfg_interrupt);
                scop_cfg_interrupt);
`else
`else
        reg     r_scop_cfg_ack;
        reg     r_scop_cfg_ack;
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
                r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
        assign  scop_cfg_ack = r_scop_cfg_ack;
        assign  scop_cfg_ack = r_scop_cfg_ack;
        assign  scop_cfg_data = 32'h000;
        assign  scop_cfg_data = 32'h000;
        assign  scop_cfg_stall= 1'b0;
        assign  scop_cfg_stall= 1'b0;
`endif
`endif
 
 
        assign  scop_interrupt = scop_cfg_interrupt;
        assign  scop_interrupt = scop_cfg_interrupt;
        assign  scop_ack   = scop_cfg_ack;
        assign  scop_ack   = scop_cfg_ack;
        assign  scop_stall = scop_cfg_stall;
        assign  scop_stall = scop_cfg_stall;
        assign  scop_data  = scop_cfg_data;
        assign  scop_data  = scop_cfg_data;
 
 
endmodule
endmodule
 
 
 
 

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