////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: busmaster.v
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// Filename: busmaster.v
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//
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//
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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//
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//
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`include "builddate.v"
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`include "builddate.v"
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//
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//
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`define INCLUDE_ZIPPY
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`define INCLUDE_ZIPPY
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`define IMPLEMENT_ONCHIP_RAM // 2804 w/o after synthesis
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`define IMPLEMENT_ONCHIP_RAM // 2804 w/o after synthesis
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`ifndef VERILATOR
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`ifndef VERILATOR
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`define FANCY_ICAP_ACCESS
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`define FANCY_ICAP_ACCESS
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`endif
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`endif
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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// `define INCLUDE_RTC // About 90 LUTs
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// `define INCLUDE_RTC // About 90 LUTs
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module busmaster(i_clk, i_rst,
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module busmaster(i_clk, i_rst,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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o_uart_rts,
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o_uart_cts,
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// The SPI Flash lines
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// The SPI Flash lines
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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// The board I/O
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// The board I/O
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i_btn, o_led, o_pwm, o_pwm_aux,
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i_btn, o_led, o_pwm, o_pwm_aux,
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// Keypad connections
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// Keypad connections
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i_kp_row, o_kp_col,
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i_kp_row, o_kp_col,
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// UART control
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// UART control
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o_uart_setup,
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o_uart_setup,
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// GPIO lines
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// GPIO lines
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i_gpio, o_gpio);
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i_gpio, o_gpio);
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parameter BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
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parameter BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
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CMOD_ZIPCPU_RESET_ADDRESS=23'h480000,
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CMOD_ZIPCPU_RESET_ADDRESS=23'h480000,
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ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
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ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_rx_stb;
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input i_rx_stb;
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input [7:0] i_rx_data;
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input [7:0] i_rx_data;
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output reg o_tx_stb;
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output reg o_tx_stb;
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output reg [7:0] o_tx_data;
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output reg [7:0] o_tx_data;
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input i_tx_busy;
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input i_tx_busy;
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output wire o_uart_rts;
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output wire o_uart_cts;
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// SPI flash control
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// SPI flash control
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output wire o_qspi_cs_n, o_qspi_sck;
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output wire o_qspi_cs_n, o_qspi_sck;
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output wire [3:0] o_qspi_dat;
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output wire [3:0] o_qspi_dat;
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input [3:0] i_qspi_dat;
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input [3:0] i_qspi_dat;
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output wire [1:0] o_qspi_mod;
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output wire [1:0] o_qspi_mod;
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// Board I/O
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// Board I/O
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input [1:0] i_btn;
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input [1:0] i_btn;
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output wire [3:0] o_led;
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output wire [3:0] o_led;
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output wire o_pwm;
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output wire o_pwm;
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output wire [1:0] o_pwm_aux;
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output wire [1:0] o_pwm_aux;
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// Keypad
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// Keypad
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input [3:0] i_kp_row;
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input [3:0] i_kp_row;
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output wire [3:0] o_kp_col;
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output wire [3:0] o_kp_col;
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// UART control
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// UART control
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output wire [29:0] o_uart_setup;
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output wire [29:0] o_uart_setup;
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// GPIO liines
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// GPIO liines
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input [15:0] i_gpio;
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input [15:0] i_gpio;
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output wire [15:0] o_gpio;
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output wire [15:0] o_gpio;
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//
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//
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//
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//
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// Master wishbone wires
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// Master wishbone wires
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//
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//
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//
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//
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wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
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wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
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wire [31:0] wb_data, wb_idata;
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wire [31:0] wb_data, wb_idata;
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wire [(BAW-1):0] wb_addr;
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wire [(BAW-1):0] wb_addr;
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wire [5:0] io_addr;
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wire [5:0] io_addr;
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assign io_addr = {
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assign io_addr = {
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wb_addr[22], // Flash
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wb_addr[22], // Flash
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wb_addr[13], // RAM
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wb_addr[13], // RAM
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wb_addr[11], // RTC
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wb_addr[11], // RTC
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wb_addr[10], // CFG
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wb_addr[10], // CFG
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wb_addr[ 9], // SCOPE
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wb_addr[ 9], // SCOPE
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wb_addr[ 8] }; // I/O
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wb_addr[ 8] }; // I/O
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// Wires going to devices
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// Wires going to devices
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// And then headed back home
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// And then headed back home
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wire w_interrupt;
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wire w_interrupt;
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// Oh, and the debug control for the ZIP CPU
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// Oh, and the debug control for the ZIP CPU
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wire zip_dbg_ack, zip_dbg_stall;
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wire zip_dbg_ack, zip_dbg_stall;
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wire [31:0] zip_dbg_data;
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wire [31:0] zip_dbg_data;
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//
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//
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//
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//
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// The BUS master (source): The ZipCPU
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// The BUS master (source): The ZipCPU
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//
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//
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//
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//
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wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
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wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
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wire [(ZA-1):0] w_zip_addr;
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wire [(ZA-1):0] w_zip_addr;
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wire [(BAW-1):0] zip_addr;
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wire [(BAW-1):0] zip_addr;
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wire [31:0] zip_data;
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wire [31:0] zip_data;
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// and then coming from devices
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// and then coming from devices
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wire zip_ack, zip_stall, zip_err;
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wire zip_ack, zip_stall, zip_err;
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wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
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wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
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wire [(BAW-1):0] dwb_addr;
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wire [(BAW-1):0] dwb_addr;
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wire [31:0] dwb_odata;
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wire [31:0] dwb_odata;
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// wire [31:0] zip_debug;
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// wire [31:0] zip_debug;
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//
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//
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// We'll define our RESET_ADDRESS to be halfway through our flash memory.
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// We'll define our RESET_ADDRESS to be halfway through our flash memory.
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// `define CMOD_ZIPCPU_RESET_ADDRESS 23'h600000
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// `define CMOD_ZIPCPU_RESET_ADDRESS 23'h600000
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//
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//
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// Ahm, No. We can actually do much better than that. Our toplevel *.bit file
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// Ahm, No. We can actually do much better than that. Our toplevel *.bit file
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// only takes up only 335kB. Let's give it some room to grow to 1024 kB. Then
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// only takes up only 335kB. Let's give it some room to grow to 1024 kB. Then
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// 23 can start our ROM at 23'h400100
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// 23 can start our ROM at 23'h400100
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//
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//
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// Not so fast. In hindsight, we really want to be able to adjust the load and
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// Not so fast. In hindsight, we really want to be able to adjust the load and
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// the program separately. So, instead, let's place our RESET address at the
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// the program separately. So, instead, let's place our RESET address at the
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// second flash erase block. That way, we can change our program code found
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// second flash erase block. That way, we can change our program code found
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// in the flash without needing to change our FPGA load and vice versa.
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// in the flash without needing to change our FPGA load and vice versa.
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//
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//
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// 23'h404000
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// 23'h404000
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zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
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zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
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thecpu(i_clk, 1'b0,
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thecpu(i_clk, 1'b0,
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// Zippys wishbone interface
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// Zippys wishbone interface
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wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data,
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wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data,
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wb_ack, wb_stall, wb_idata, wb_err,
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wb_ack, wb_stall, wb_idata, wb_err,
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w_interrupt, zip_cpu_int,
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w_interrupt, zip_cpu_int,
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// Debug wishbone interface
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// Debug wishbone interface
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1'b0, 1'b0,1'b0, 1'b0, 32'h00,
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1'b0, 1'b0,1'b0, 1'b0, 32'h00,
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zip_dbg_ack, zip_dbg_stall, zip_dbg_data);
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zip_dbg_ack, zip_dbg_stall, zip_dbg_data);
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generate
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generate
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if (ZA < BAW)
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if (ZA < BAW)
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assign wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
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assign wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
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else
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else
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assign wb_addr = w_zip_addr;
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assign wb_addr = w_zip_addr;
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endgenerate
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endgenerate
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wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
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wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
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rtc_sel, none_sel, many_sel;
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rtc_sel, none_sel, many_sel;
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wire flash_ack, scop_ack, cfg_ack, mem_ack;
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wire flash_ack, scop_ack, cfg_ack, mem_ack;
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wire rtc_ack, rtc_stall;
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wire rtc_ack, rtc_stall;
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`ifdef INCLUDE_RTC
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`ifdef INCLUDE_RTC
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assign rtc_stall = 1'b0;
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assign rtc_stall = 1'b0;
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`endif
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`endif
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wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
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wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
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reg io_ack;
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reg io_ack;
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wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
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wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
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spio_data, gpio_data, uart_data;
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spio_data, gpio_data, uart_data;
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reg [31:0] io_data;
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reg [31:0] io_data;
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reg [(BAW-1):0] bus_err_addr;
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reg [(BAW-1):0] bus_err_addr;
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assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
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assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
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`ifdef INCLUDE_RTC
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`ifdef INCLUDE_RTC
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||(rtc_ack)
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||(rtc_ack)
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`endif
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`endif
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||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
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||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
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assign wb_stall = ((io_sel)&&(io_stall))
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assign wb_stall = ((io_sel)&&(io_stall))
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||((scop_sel)&&(scop_stall))
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||((scop_sel)&&(scop_stall))
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||((cfg_sel)&&(cfg_stall))
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||((cfg_sel)&&(cfg_stall))
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||((mem_sel)&&(mem_stall))
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||((mem_sel)&&(mem_stall))
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`ifdef INCLUDE_RTC
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`ifdef INCLUDE_RTC
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||((rtc_sel)&&(rtc_stall))
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||((rtc_sel)&&(rtc_stall))
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`endif
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`endif
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||((flash_sel||flctl_sel)&&(flash_stall));
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||((flash_sel||flctl_sel)&&(flash_stall));
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// (none_sel)&&(1'b0)
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// (none_sel)&&(1'b0)
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/*
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/*
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assign wb_idata = (io_ack)?io_data
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assign wb_idata = (io_ack)?io_data
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: ((scop_ack)?scop_data
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: ((scop_ack)?scop_data
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: ((cfg_ack)?cfg_data
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: ((cfg_ack)?cfg_data
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: ((mem_ack)?mem_data
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: ((mem_ack)?mem_data
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: ((flash_ack)?flash_data
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: ((flash_ack)?flash_data
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: 32'h00))));
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: 32'h00))));
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*/
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*/
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assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
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assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
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: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
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: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
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: ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
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: ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
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assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
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assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
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// Addresses ...
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// Addresses ...
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// 0000 xxxx configuration/control registers
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// 0000 xxxx configuration/control registers
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// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
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// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
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assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
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assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
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assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
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assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
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assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
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assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
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assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1));
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assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1));
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// zip_sel is not on the bus at this point
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// zip_sel is not on the bus at this point
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`ifdef INCLUDE_RTC
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`ifdef INCLUDE_RTC
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assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
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assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
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`endif
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`endif
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assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
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assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
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assign flash_sel=((wb_cyc)&&(io_addr[5]));
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assign flash_sel=((wb_cyc)&&(io_addr[5]));
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|
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assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
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assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
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/*
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/*
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assign many_sel =((wb_cyc)&&(wb_stb)&&(
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assign many_sel =((wb_cyc)&&(wb_stb)&&(
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{3'h0, io_sel}
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{3'h0, io_sel}
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+{3'h0, flctl_sel}
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+{3'h0, flctl_sel}
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+{3'h0, scop_sel}
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+{3'h0, scop_sel}
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+{3'h0, cfg_sel}
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+{3'h0, cfg_sel}
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+{3'h0, rtc_sel}
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+{3'h0, rtc_sel}
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+{3'h0, mem_sel}
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+{3'h0, mem_sel}
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+{3'h0, flash_sel} > 1));
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+{3'h0, flash_sel} > 1));
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*/
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*/
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assign many_sel = 1'b0;
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assign many_sel = 1'b0;
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|
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wire many_ack;
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wire many_ack;
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assign many_ack =((wb_cyc)&&(
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assign many_ack =((wb_cyc)&&(
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{3'h0, io_ack}
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{3'h0, io_ack}
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+{3'h0, scop_ack}
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+{3'h0, scop_ack}
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+{3'h0, cfg_ack}
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+{3'h0, cfg_ack}
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`ifdef INCLUDE_RTC
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`ifdef INCLUDE_RTC
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+{3'h0, rtc_ack}
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+{3'h0, rtc_ack}
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`endif
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`endif
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+{3'h0, mem_ack}
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+{3'h0, mem_ack}
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+{3'h0, flash_ack} > 1));
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+{3'h0, flash_ack} > 1));
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|
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wire flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
|
wire flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
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rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
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rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
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|
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|
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//
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//
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//
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//
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//
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//
|
reg rx_rdy;
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reg rx_rdy;
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wire [10:0] int_vector;
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wire [10:0] int_vector;
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assign int_vector = { gpio_int, pwm_int, keypad_int,
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assign int_vector = { gpio_int, pwm_int, keypad_int,
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~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
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~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
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rtc_interrupt, scop_interrupt,
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rtc_interrupt, scop_interrupt,
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wb_err, button_int };
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wb_err, button_int };
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|
|
wire [31:0] pic_data;
|
wire [31:0] pic_data;
|
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
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icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
|
&&(wb_addr[3:0]==4'h0)&&(wb_we),
|
&&(wb_addr[3:0]==4'h0)&&(wb_we),
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wb_data, pic_data, int_vector, w_interrupt);
|
wb_data, pic_data, int_vector, w_interrupt);
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|
|
initial bus_err_addr = 0; // `DATESTAMP;
|
initial bus_err_addr = 0; // `DATESTAMP;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wb_err)
|
if (wb_err)
|
bus_err_addr <= wb_addr;
|
bus_err_addr <= wb_addr;
|
|
|
wire [31:0] timer_a, timer_b;
|
wire [31:0] timer_a, timer_b;
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
ziptimer #(32,31)
|
ziptimer #(32,31)
|
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
|
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
wb_we, wb_data, zta_ack, zta_stall, timer_a,
|
wb_we, wb_data, zta_ack, zta_stall, timer_a,
|
tmra_int);
|
tmra_int);
|
ziptimer #(32,31)
|
ziptimer #(32,31)
|
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
|
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
tmrb_int);
|
tmrb_int);
|
|
|
wire [31:0] rtc_data;
|
wire [31:0] rtc_data;
|
`ifdef INCLUDE_RTC
|
`ifdef INCLUDE_RTC
|
wire rtcd_ack, rtcd_stall, ppd;
|
wire rtcd_ack, rtcd_stall, ppd;
|
// rtcdate thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
|
// rtcdate thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
|
// wb_data, rtcd_ack, rtcd_stall, date_data);
|
// wb_data, rtcd_ack, rtcd_stall, date_data);
|
reg r_rtc_ack;
|
reg r_rtc_ack;
|
initial r_rtc_ack = 1'b0;
|
initial r_rtc_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_rtc_ack <= ((wb_stb)&&(rtc_sel));
|
r_rtc_ack <= ((wb_stb)&&(rtc_sel));
|
assign rtc_ack = r_rtc_ack;
|
assign rtc_ack = r_rtc_ack;
|
|
|
rtclight
|
rtclight
|
#(23'h35afe5,23,0,0) // 80 MHz clock
|
#(23'h35afe5,23,0,0) // 80 MHz clock
|
thetime(i_clk, wb_cyc,
|
thetime(i_clk, wb_cyc,
|
((wb_stb)&&(rtc_sel)), wb_we,
|
((wb_stb)&&(rtc_sel)), wb_we,
|
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
|
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
|
rtc_interrupt, ppd);
|
rtc_interrupt, ppd);
|
`else
|
`else
|
assign rtc_interrupt = 1'b0;
|
assign rtc_interrupt = 1'b0;
|
assign rtc_data = 32'h00;
|
assign rtc_data = 32'h00;
|
assign rtc_ack = 1'b0;
|
assign rtc_ack = 1'b0;
|
`endif
|
`endif
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
case(wb_addr[3:0])
|
case(wb_addr[3:0])
|
4'h0: io_data <= pic_data;
|
4'h0: io_data <= pic_data;
|
4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
|
4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
|
4'h2: io_data <= timer_a;
|
4'h2: io_data <= timer_a;
|
4'h3: io_data <= timer_b;
|
4'h3: io_data <= timer_b;
|
4'h4: io_data <= pwm_data;
|
4'h4: io_data <= pwm_data;
|
4'h5: io_data <= spio_data;
|
4'h5: io_data <= spio_data;
|
4'h6: io_data <= gpio_data;
|
4'h6: io_data <= gpio_data;
|
4'h7: io_data <= uart_data;
|
4'h7: io_data <= uart_data;
|
default: io_data <= `DATESTAMP;
|
default: io_data <= `DATESTAMP;
|
// 4'h8: io_data <= `DATESTAMP;
|
// 4'h8: io_data <= `DATESTAMP;
|
endcase
|
endcase
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
|
io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
|
assign io_stall = 1'b0;
|
assign io_stall = 1'b0;
|
|
|
wire pwm_ack, pwm_stall;
|
wire pwm_ack, pwm_stall;
|
wbpwmaudio theaudio(i_clk, wb_cyc,
|
wbpwmaudio #(14'd10000,2,0,14)
|
((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)), wb_we,
|
theaudio(i_clk, wb_cyc,
|
1'b0, wb_data,
|
((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
|
pwm_ack, pwm_stall, pwm_data, o_pwm, o_pwm_aux,
|
wb_we, 1'b0, wb_data,
|
|
pwm_ack, pwm_stall, pwm_data, o_pwm,
|
|
o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
|
pwm_int);
|
pwm_int);
|
|
|
//
|
//
|
// Special Purpose I/O: Keypad, button, LED status and control
|
// Special Purpose I/O: Keypad, button, LED status and control
|
//
|
//
|
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
|
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
|
wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
|
wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
|
keypad_int, button_int);
|
keypad_int, button_int);
|
|
|
//
|
//
|
// General purpose (sort of) I/O: (Bottom two bits robbed in each
|
// General purpose (sort of) I/O: (Bottom two bits robbed in each
|
// direction for an I2C link at the toplevel.v design)
|
// direction for an I2C link at the toplevel.v design)
|
//
|
//
|
wbgpio #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
|
wbgpio #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
|
wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
|
wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
|
|
|
//
|
//
|
//
|
//
|
// Rudimentary serial port control
|
// Rudimentary serial port control
|
//
|
//
|
reg [7:0] r_rx_data;
|
reg [7:0] r_rx_data;
|
// Baud rate is set by clock rate / baud rate.
|
// Baud rate is set by clock rate / baud rate.
|
// Thus, 80MHz / 115200MBau
|
// Thus, 80MHz / 115200MBau
|
// = 694.4, or about 0x2b6.
|
// = 694.4, or about 0x2b6.
|
// although the CPU might struggle to keep up at this speed without a
|
// although the CPU might struggle to keep up at this speed without a
|
// hardware buffer.
|
// hardware buffer.
|
//
|
//
|
// We'll add the flag for two stop bits.
|
// We'll add the flag for two stop bits.
|
// assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
|
// assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
|
assign o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
|
assign o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
|
|
|
initial o_tx_stb = 1'b0;
|
initial o_tx_stb = 1'b0;
|
initial o_tx_data = 8'h00;
|
initial o_tx_data = 8'h00;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
|
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
|
begin
|
begin
|
o_tx_data <= wb_data[7:0];
|
o_tx_data <= wb_data[7:0];
|
o_tx_stb <= 1'b1;
|
o_tx_stb <= 1'b1;
|
end
|
end
|
else if ((o_tx_stb)&&(~i_tx_busy))
|
else if ((o_tx_stb)&&(~i_tx_busy))
|
o_tx_stb <= 1'b0;
|
o_tx_stb <= 1'b0;
|
initial rx_rdy = 1'b0;
|
initial rx_rdy = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rx_stb)
|
if (i_rx_stb)
|
r_rx_data <= i_rx_data;
|
r_rx_data <= i_rx_data;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
|
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
|
rx_rdy <= i_rx_stb;
|
rx_rdy <= i_rx_stb;
|
else if (i_rx_stb)
|
else if (i_rx_stb)
|
rx_rdy <= (rx_rdy | i_rx_stb);
|
rx_rdy <= (rx_rdy | i_rx_stb);
|
end
|
end
|
assign o_uart_rts = (~rx_rdy);
|
assign o_uart_cts = (~rx_rdy);
|
assign uart_data = { 23'h0, ~rx_rdy, r_rx_data };
|
assign uart_data = { 23'h0, ~rx_rdy, r_rx_data };
|
//
|
//
|
// uart_ack gets returned as part of io_ack, since that happens when
|
// uart_ack gets returned as part of io_ack, since that happens when
|
// io_sel and wb_stb are defined
|
// io_sel and wb_stb are defined
|
//
|
//
|
// always @(posedge i_clk)
|
// always @(posedge i_clk)
|
// uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
|
// uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
|
|
|
|
|
|
|
//
|
//
|
// FLASH MEMORY CONFIGURATION ACCESS
|
// FLASH MEMORY CONFIGURATION ACCESS
|
//
|
//
|
wbqspiflash #(24) flashmem(i_clk,
|
wbqspiflash #(24) flashmem(i_clk,
|
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_addr[(24-3):0], wb_data,
|
wb_addr[(24-3):0], wb_data,
|
flash_ack, flash_stall, flash_data,
|
flash_ack, flash_stall, flash_data,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
flash_interrupt);
|
flash_interrupt);
|
|
|
//
|
//
|
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
|
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
|
//
|
//
|
wire [31:0] cfg_scope;
|
wire [31:0] cfg_scope;
|
`ifdef FANCY_ICAP_ACCESS
|
`ifdef FANCY_ICAP_ACCESS
|
wbicape6 fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
|
wbicape6 fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
|
wb_addr[5:0], wb_data,
|
wb_addr[5:0], wb_data,
|
cfg_ack, cfg_stall, cfg_data,
|
cfg_ack, cfg_stall, cfg_data,
|
cfg_scope);
|
cfg_scope);
|
`else
|
`else
|
reg r_cfg_ack;
|
reg r_cfg_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
|
r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
|
assign cfg_ack = r_cfg_ack;
|
assign cfg_ack = r_cfg_ack;
|
assign cfg_stall = 1'b0;
|
assign cfg_stall = 1'b0;
|
assign cfg_data = 32'h00;
|
assign cfg_data = 32'h00;
|
assign cfg_scope = 32'h00;
|
assign cfg_scope = 32'h00;
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
// ON-CHIP RAM MEMORY ACCESS
|
// ON-CHIP RAM MEMORY ACCESS
|
//
|
//
|
`ifdef IMPLEMENT_ONCHIP_RAM
|
`ifdef IMPLEMENT_ONCHIP_RAM
|
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
|
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
|
`else
|
`else
|
assign mem_data = 32'h00;
|
assign mem_data = 32'h00;
|
assign mem_stall = 1'b0;
|
assign mem_stall = 1'b0;
|
reg r_mem_ack;
|
reg r_mem_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
|
r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
|
assign mem_ack = r_mem_ack;
|
assign mem_ack = r_mem_ack;
|
`endif
|
`endif
|
|
|
//
|
//
|
//
|
//
|
// WISHBONE SCOPE
|
// WISHBONE SCOPE
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
wire [31:0] scop_cfg_data;
|
wire [31:0] scop_cfg_data;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
`ifdef DBG_SCOPE
|
`ifdef DBG_SCOPE
|
wire scop_cfg_trigger;
|
wire scop_cfg_trigger;
|
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
|
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
|
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
|
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
|
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
scop_cfg_interrupt);
|
scop_cfg_interrupt);
|
`else
|
`else
|
reg r_scop_cfg_ack;
|
reg r_scop_cfg_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
|
r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
|
assign scop_cfg_ack = r_scop_cfg_ack;
|
assign scop_cfg_ack = r_scop_cfg_ack;
|
assign scop_cfg_data = 32'h000;
|
assign scop_cfg_data = 32'h000;
|
assign scop_cfg_stall= 1'b0;
|
assign scop_cfg_stall= 1'b0;
|
`endif
|
`endif
|
|
|
assign scop_interrupt = scop_cfg_interrupt;
|
assign scop_interrupt = scop_cfg_interrupt;
|
assign scop_ack = scop_cfg_ack;
|
assign scop_ack = scop_cfg_ack;
|
assign scop_stall = scop_cfg_stall;
|
assign scop_stall = scop_cfg_stall;
|
assign scop_data = scop_cfg_data;
|
assign scop_data = scop_cfg_data;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
