| Line 44... |
Line 44... |
//
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//
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`define IMPLEMENT_ONCHIP_RAM
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`define IMPLEMENT_ONCHIP_RAM
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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// `define COMPRESSED_SCOPE
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// `define COMPRESSED_SCOPE
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`define HAS_RXUART
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`define INCLUDE_CPU_RESET_LOGIC
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`define INCLUDE_CPU_RESET_LOGIC
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`define LOWLOGIC_FLASH // Saves about 154 LUTs
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`define USE_LITE_UART // Saves about 55 LUTs
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module busmaster(i_clk, i_rst,
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module busmaster(i_clk, i_rst,
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i_uart, o_uart_rts_n, o_uart, i_uart_cts_n,
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i_uart, o_uart_rts_n, o_uart, i_uart_cts_n,
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// The SPI Flash lines
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// The SPI Flash lines
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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// The board I/O
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// The board I/O
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| Line 73... |
Line 76... |
input i_clk, i_rst;
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input i_clk, i_rst;
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// UART parameters
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// UART parameters
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input i_uart, i_uart_cts_n;
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input i_uart, i_uart_cts_n;
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output wire o_uart, o_uart_rts_n;
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output wire o_uart, o_uart_rts_n;
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// SPI flash control
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// SPI flash control
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output wire o_qspi_cs_n, o_qspi_sck;
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output wire o_qspi_cs_n;
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`ifdef LOWLOGIC_FLASH
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output wire [1:0] o_qspi_sck;
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`else
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output wire o_qspi_sck;
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`endif
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output wire [3:0] o_qspi_dat;
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output wire [3:0] o_qspi_dat;
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input [3:0] i_qspi_dat;
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input [3:0] i_qspi_dat;
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output wire [1:0] o_qspi_mod;
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output wire [1:0] o_qspi_mod;
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// Board I/O
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// Board I/O
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input [1:0] i_btn;
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input [1:0] i_btn;
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| Line 138... |
Line 146... |
r_button <= x_button;
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r_button <= x_button;
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btn_reset <= ((r_button)&&(zip_cpu_int))||(watchdog_int);
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btn_reset <= ((r_button)&&(zip_cpu_int))||(watchdog_int);
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end
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end
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assign cpu_reset = btn_reset;
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assign cpu_reset = btn_reset;
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`else
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`else
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assign cpu_reset = 1'b0;
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assign cpu_reset = (watchdog_int);
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`endif
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`endif
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zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
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zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
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swic(i_clk, btn_reset, // 1'b0,
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swic(i_clk, cpu_reset, // 1'b0,
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// Zippys wishbone interface
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// Zippys wishbone interface
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wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data, wb_sel,
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wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data, wb_sel,
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wb_ack, wb_stall, wb_idata, wb_err,
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wb_ack, wb_stall, wb_idata, wb_err,
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w_interrupt, zip_cpu_int,
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w_interrupt, zip_cpu_int,
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// Debug wishbone interface -- not really used
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// Debug wishbone interface -- not really used
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| Line 435... |
Line 443... |
wire [3:0] w_led;
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wire [3:0] w_led;
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spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),
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spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),
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wb_we, wb_data, spio_data,
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wb_we, wb_data, spio_data,
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o_kp_col, i_kp_row, i_btn, w_led,
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o_kp_col, i_kp_row, i_btn, w_led,
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keypad_int, button_int);
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keypad_int, button_int);
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assign o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,w_led[1:0] };
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assign o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,
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w_led[1], w_led[0] };
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//
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//
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// General purpose (sort of) I/O: (Bottom two bits robbed in each
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// General purpose (sort of) I/O: (Bottom two bits robbed in each
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// direction for an I2C link at the toplevel.v design)
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// direction for an I2C link at the toplevel.v design)
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//
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//
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| Line 457... |
Line 466... |
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, rx_stb;
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wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, rx_stb;
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wire [7:0] rx_data;
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wire [7:0] rx_data;
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//
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//
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assign uart_setup = UART_SETUP;
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assign uart_setup = UART_SETUP;
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//
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//
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`ifdef HAS_RXUART
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`ifdef USE_LITE_UART
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rxuartlite #(UART_SETUP[23:0])
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rcvuart(i_clk, i_uart, rx_stb, rx_data);
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assign rx_break = 1'b0;
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assign rx_parity_err = 1'b0;
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assign rx_frame_err = 1'b0;
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assign rx_ck_uart = 1'b0;
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`else
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rxuart #(UART_SETUP)
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rxuart #(UART_SETUP)
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rcvuart(i_clk, 1'b0, uart_setup, i_uart, rx_stb, rx_data,
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rcvuart(i_clk, 1'b0, uart_setup, i_uart, rx_stb, rx_data,
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rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
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rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
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`endif
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`else
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assign rx_break = 1'b0;
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assign rx_parity_err = 1'b0;
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assign rx_frame_err = 1'b0;
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assign rx_ck_uart = 1'b0;
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assign rx_stb = 1'b0;
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assign rx_data = 8'h0;
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`endif
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//
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//
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wire tx_break, tx_busy;
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wire tx_break, tx_busy;
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reg tx_stb;
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reg tx_stb;
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reg [7:0] tx_data;
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reg [7:0] tx_data;
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assign tx_break = 1'b0;
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assign tx_break = 1'b0;
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`ifdef USE_LITE_UART
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txuartlite #(UART_SETUP[23:0])
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tcvuart(i_clk, tx_stb, tx_data, o_uart, tx_busy);
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`else
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txuart #(UART_SETUP)
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txuart #(UART_SETUP)
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tcvuart(i_clk, 1'b0, uart_setup, tx_break, tx_stb, tx_data,
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tcvuart(i_clk, 1'b0, uart_setup, tx_break, tx_stb, tx_data,
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i_uart_cts_n, o_uart, tx_busy);
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i_uart_cts_n, o_uart, tx_busy);
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`endif
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//
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//
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// Rudimentary serial port control
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// Rudimentary serial port control
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//
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//
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reg [7:0] r_rx_data;
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reg [7:0] r_rx_data;
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| Line 485... |
Line 517... |
tx_data <= wb_data[7:0];
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tx_data <= wb_data[7:0];
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tx_stb <= 1'b1;
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tx_stb <= 1'b1;
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end
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end
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else if ((tx_stb)&&(!tx_busy))
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else if ((tx_stb)&&(!tx_busy))
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tx_stb <= 1'b0;
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tx_stb <= 1'b0;
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`ifdef HAS_RXUART
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initial rx_rdy = 1'b0;
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initial rx_rdy = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (rx_stb)
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if (rx_stb)
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r_rx_data <= rx_data;
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r_rx_data <= rx_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(!wb_we))
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if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(!wb_we))
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rx_rdy <= rx_stb;
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rx_rdy <= rx_stb;
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else if (rx_stb)
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else
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rx_rdy <= (rx_rdy | rx_stb);
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rx_rdy <= (rx_rdy | rx_stb);
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end
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end
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assign o_uart_rts_n = (rx_rdy);
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assign o_uart_rts_n = (rx_rdy);
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assign uart_data = { 23'h0, !rx_rdy, r_rx_data };
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assign uart_data = { 23'h0, !rx_rdy, r_rx_data };
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`else
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assign o_uart_rts_n = 1'b1;
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assign uart_data = 32'h00;
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`endif
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//
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//
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// uart_ack gets returned as part of io_ack, since that happens when
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// uart_ack gets returned as part of io_ack, since that happens when
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// io_sel and wb_stb are defined
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// io_sel and wb_stb are defined
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//
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//
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// always @(posedge i_clk)
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// always @(posedge i_clk)
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| Line 511... |
Line 548... |
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//
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//
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// FLASH MEMORY CONFIGURATION ACCESS
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// FLASH MEMORY CONFIGURATION ACCESS
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//
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//
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`ifdef FLASH_ACCESS
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`ifdef FLASH_ACCESS
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`ifdef LOWLOGIC_FLASH
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qflashxpress flashmem(i_clk,
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wb_cyc,(wb_stb)&&(flash_sel),
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wb_addr[(LGFLASHSZ-3):0],
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flash_ack, flash_stall, flash_data,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat);
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assign flash_interrupt = 1'b0;
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`else
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wbqspiflash #(LGFLASHSZ) flashmem(i_clk,
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wbqspiflash #(LGFLASHSZ) flashmem(i_clk,
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wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
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wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
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wb_addr[(LGFLASHSZ-3):0], wb_data,
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wb_addr[(LGFLASHSZ-3):0], wb_data,
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flash_ack, flash_stall, flash_data,
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flash_ack, flash_stall, flash_data,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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flash_interrupt);
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flash_interrupt);
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`endif
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`else
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`else
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reg r_flash_ack;
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reg r_flash_ack;
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initial r_flash_ack = 1'b0;
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initial r_flash_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
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r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
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