////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: busmaster.v
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// Filename: busmaster.v
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//
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//
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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//
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//
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// Purpose: This is the highest level, simulatable, file in the S6SoC
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// Purpose: This is the highest level, simulatable, file in the S6SoC
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// project--of that portion of the project that includes the
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// project--of that portion of the project that includes the
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// ZipCPU. This portion therefore contains references to all of the
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// ZipCPU. This portion therefore contains references to all of the
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// masters (ZipCPU) and slaves (flash, block RAM, I/O, Scope) on the
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// masters (ZipCPU) and slaves (flash, block RAM, I/O, Scope) on the
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// wishbone bus, and connects them all together. Hence, this contains
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// wishbone bus, and connects them all together. Hence, this contains
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// the wishbone interconnect logic as well.
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// the wishbone interconnect logic as well.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`include "builddate.v"
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`include "builddate.v"
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//
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//
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`define IMPLEMENT_ONCHIP_RAM
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`define IMPLEMENT_ONCHIP_RAM
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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// `define COMPRESSED_SCOPE
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// `define COMPRESSED_SCOPE
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`define HAS_RXUART
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`define INCLUDE_CPU_RESET_LOGIC
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`define INCLUDE_CPU_RESET_LOGIC
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`define LOWLOGIC_FLASH // Saves about 154 LUTs
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`define USE_LITE_UART // Saves about 55 LUTs
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module busmaster(i_clk, i_rst,
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module busmaster(i_clk, i_rst,
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i_uart, o_uart_rts_n, o_uart, i_uart_cts_n,
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i_uart, o_uart_rts_n, o_uart, i_uart_cts_n,
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// The SPI Flash lines
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// The SPI Flash lines
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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// The board I/O
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// The board I/O
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i_btn, o_led, o_pwm, o_pwm_aux,
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i_btn, o_led, o_pwm, o_pwm_aux,
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// Keypad connections
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// Keypad connections
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i_kp_row, o_kp_col,
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i_kp_row, o_kp_col,
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// GPIO lines
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// GPIO lines
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i_gpio, o_gpio);
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i_gpio, o_gpio);
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parameter BUS_ADDRESS_WIDTH=23,
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parameter BUS_ADDRESS_WIDTH=23,
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ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
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ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
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CMOD_ZIPCPU_RESET_ADDRESS=32'h1200000,
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CMOD_ZIPCPU_RESET_ADDRESS=32'h1200000,
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UART_SETUP = 31'd25;
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UART_SETUP = 31'd25;
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localparam ZA=ZIP_ADDRESS_WIDTH,
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localparam ZA=ZIP_ADDRESS_WIDTH,
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BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
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BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
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// 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from
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// 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from
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// 0 to 11. As with many other devices, the wb_cyc line is more for
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// 0 to 11. As with many other devices, the wb_cyc line is more for
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// form than anything else--it is ignored by the memory itself.
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// form than anything else--it is ignored by the memory itself.
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localparam LGMEMSZ=14; // Takes 8 BLKRAM16 elements for LGMEMSZ=14
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localparam LGMEMSZ=14; // Takes 8 BLKRAM16 elements for LGMEMSZ=14
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// As with the memory size, the flash size is also measured in log_2 of
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// As with the memory size, the flash size is also measured in log_2 of
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// the number of bytes.
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// the number of bytes.
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localparam LGFLASHSZ = 24;
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localparam LGFLASHSZ = 24;
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input i_clk, i_rst;
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input i_clk, i_rst;
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// UART parameters
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// UART parameters
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input i_uart, i_uart_cts_n;
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input i_uart, i_uart_cts_n;
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output wire o_uart, o_uart_rts_n;
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output wire o_uart, o_uart_rts_n;
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// SPI flash control
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// SPI flash control
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output wire o_qspi_cs_n, o_qspi_sck;
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output wire o_qspi_cs_n;
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`ifdef LOWLOGIC_FLASH
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output wire [1:0] o_qspi_sck;
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`else
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output wire o_qspi_sck;
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`endif
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output wire [3:0] o_qspi_dat;
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output wire [3:0] o_qspi_dat;
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input [3:0] i_qspi_dat;
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input [3:0] i_qspi_dat;
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output wire [1:0] o_qspi_mod;
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output wire [1:0] o_qspi_mod;
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// Board I/O
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// Board I/O
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input [1:0] i_btn;
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input [1:0] i_btn;
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output wire [3:0] o_led;
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output wire [3:0] o_led;
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output wire o_pwm;
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output wire o_pwm;
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output wire [1:0] o_pwm_aux;
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output wire [1:0] o_pwm_aux;
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// Keypad
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// Keypad
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input [3:0] i_kp_row;
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input [3:0] i_kp_row;
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output wire [3:0] o_kp_col;
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output wire [3:0] o_kp_col;
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// GPIO liines
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// GPIO liines
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input [15:0] i_gpio;
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input [15:0] i_gpio;
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output wire [15:0] o_gpio;
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output wire [15:0] o_gpio;
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//
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//
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//
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//
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// Master wishbone wires
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// Master wishbone wires
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//
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//
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//
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//
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wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
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wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
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wire [31:0] wb_data, wb_idata;
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wire [31:0] wb_data, wb_idata;
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wire [3:0] wb_sel;
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wire [3:0] wb_sel;
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wire [(BAW-1):0] wb_addr;
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wire [(BAW-1):0] wb_addr;
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// Wires going to devices
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// Wires going to devices
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// And then headed back home
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// And then headed back home
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wire w_interrupt;
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wire w_interrupt;
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// Oh, and the debug control for the ZIP CPU
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// Oh, and the debug control for the ZIP CPU
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wire zip_dbg_ack, zip_dbg_stall;
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wire zip_dbg_ack, zip_dbg_stall;
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wire [31:0] zip_dbg_data;
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wire [31:0] zip_dbg_data;
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//
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//
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//
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//
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// The BUS master (source): The ZipCPU
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// The BUS master (source): The ZipCPU
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//
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//
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//
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//
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wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
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wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
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wire [(ZA-1):0] w_zip_addr;
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wire [(ZA-1):0] w_zip_addr;
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wire [(BAW-1):0] zip_addr;
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wire [(BAW-1):0] zip_addr;
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wire [31:0] zip_data, zip_scope_data;
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wire [31:0] zip_data, zip_scope_data;
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// and then coming from devices
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// and then coming from devices
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wire zip_ack, zip_stall, zip_err;
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wire zip_ack, zip_stall, zip_err;
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wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
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wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
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wire [(BAW-1):0] dwb_addr;
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wire [(BAW-1):0] dwb_addr;
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wire [31:0] dwb_odata;
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wire [31:0] dwb_odata;
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wire cpu_reset, watchdog_int;
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wire cpu_reset, watchdog_int;
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//
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//
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`ifdef INCLUDE_CPU_RESET_LOGIC
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`ifdef INCLUDE_CPU_RESET_LOGIC
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reg btn_reset, x_button, r_button;
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reg btn_reset, x_button, r_button;
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initial btn_reset = 1'b0;
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initial btn_reset = 1'b0;
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initial x_button = 1'b0;
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initial x_button = 1'b0;
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initial r_button = 1'b0;
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initial r_button = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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x_button <= i_btn[1];
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x_button <= i_btn[1];
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r_button <= x_button;
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r_button <= x_button;
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btn_reset <= ((r_button)&&(zip_cpu_int))||(watchdog_int);
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btn_reset <= ((r_button)&&(zip_cpu_int))||(watchdog_int);
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end
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end
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assign cpu_reset = btn_reset;
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assign cpu_reset = btn_reset;
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`else
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`else
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assign cpu_reset = 1'b0;
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assign cpu_reset = (watchdog_int);
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`endif
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`endif
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zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
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zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
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swic(i_clk, btn_reset, // 1'b0,
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swic(i_clk, cpu_reset, // 1'b0,
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// Zippys wishbone interface
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// Zippys wishbone interface
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wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data, wb_sel,
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wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data, wb_sel,
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wb_ack, wb_stall, wb_idata, wb_err,
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wb_ack, wb_stall, wb_idata, wb_err,
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w_interrupt, zip_cpu_int,
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w_interrupt, zip_cpu_int,
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// Debug wishbone interface -- not really used
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// Debug wishbone interface -- not really used
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1'b0, 1'b0,1'b0, 1'b0, 32'h00,
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1'b0, 1'b0,1'b0, 1'b0, 32'h00,
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zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
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zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
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zip_scope_data);
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zip_scope_data);
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generate
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generate
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if (ZA < BAW)
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if (ZA < BAW)
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assign wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
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assign wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
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else
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else
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assign wb_addr = w_zip_addr;
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assign wb_addr = w_zip_addr;
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endgenerate
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endgenerate
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// Signals to build/detect bus errors
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// Signals to build/detect bus errors
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wire none_sel, many_sel;
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wire none_sel, many_sel;
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|
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wire io_sel, flash_sel, flctl_sel, scop_sel, mem_sel;
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wire io_sel, flash_sel, flctl_sel, scop_sel, mem_sel;
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wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
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wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
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wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
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wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
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reg io_ack;
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reg io_ack;
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wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
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wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
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spio_data, gpio_data, uart_data;
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spio_data, gpio_data, uart_data;
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reg [31:0] io_data;
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reg [31:0] io_data;
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reg [(BAW-1):0] bus_err_addr;
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reg [(BAW-1):0] bus_err_addr;
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//
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//
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// wb_ack
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// wb_ack
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//
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//
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// The returning wishbone ack is equal to the OR of every component that
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// The returning wishbone ack is equal to the OR of every component that
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// might possibly produce an acknowledgement, gated by the CYC line. To
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// might possibly produce an acknowledgement, gated by the CYC line. To
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// add new components, OR their acknowledgements in here.
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// add new components, OR their acknowledgements in here.
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//
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//
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// Note the reference to none_sel. If nothing is selected, the result
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// Note the reference to none_sel. If nothing is selected, the result
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// is an error. Here, we do nothing more than insure that the erroneous
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// is an error. Here, we do nothing more than insure that the erroneous
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// request produces an ACK ... if it was ever made, rather than stalling
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// request produces an ACK ... if it was ever made, rather than stalling
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// the bus.
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// the bus.
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//
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//
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|
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assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)
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assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)
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||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
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||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
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|
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//
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//
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// wb_stall
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// wb_stall
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//
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//
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// The returning wishbone stall line really depends upon what device
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// The returning wishbone stall line really depends upon what device
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// is requested. Thus, if a particular device is selected, we return
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// is requested. Thus, if a particular device is selected, we return
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// the stall line for that device.
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// the stall line for that device.
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//
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//
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// To add a new device, simply and that devices select and stall lines
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// To add a new device, simply and that devices select and stall lines
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// together, and OR the result with the massive OR logic below.
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// together, and OR the result with the massive OR logic below.
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//
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//
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assign wb_stall = ((io_sel)&&(io_stall))
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assign wb_stall = ((io_sel)&&(io_stall))
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||((scop_sel)&&(scop_stall))
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||((scop_sel)&&(scop_stall))
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||((mem_sel)&&(mem_stall))
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||((mem_sel)&&(mem_stall))
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||((flash_sel||flctl_sel)&&(flash_stall));
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||((flash_sel||flctl_sel)&&(flash_stall));
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// (none_sel)&&(1'b0)
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// (none_sel)&&(1'b0)
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|
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//
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//
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// wb_idata
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// wb_idata
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//
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//
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// This is the data returned on the bus. Here, we select between a
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// This is the data returned on the bus. Here, we select between a
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// series of bus sources to select what data to return. The basic
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// series of bus sources to select what data to return. The basic
|
// logic is simply this: the data we return is the data for which the
|
// logic is simply this: the data we return is the data for which the
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// ACK line is high.
|
// ACK line is high.
|
//
|
//
|
// The last item on the list is chosen by default if no other ACK's are
|
// The last item on the list is chosen by default if no other ACK's are
|
// true. Although we might choose to return zeros in that case, by
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// true. Although we might choose to return zeros in that case, by
|
// returning something we can skimp a touch on the logic.
|
// returning something we can skimp a touch on the logic.
|
//
|
//
|
// To add another device, add another ack check, and another closing
|
// To add another device, add another ack check, and another closing
|
// parenthesis.
|
// parenthesis.
|
//
|
//
|
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
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assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
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: ((mem_ack)?(mem_data)
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: ((mem_ack)?(mem_data)
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: flash_data);
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: flash_data);
|
|
|
//
|
//
|
// wb_err
|
// wb_err
|
//
|
//
|
// This is the bus error signal. It should never be true, but practice
|
// This is the bus error signal. It should never be true, but practice
|
// teaches us otherwise. Here, we allow for three basic errors:
|
// teaches us otherwise. Here, we allow for three basic errors:
|
//
|
//
|
// 1. STB is true, but no devices are selected
|
// 1. STB is true, but no devices are selected
|
//
|
//
|
// This is the null pointer reference bug. If you try to access
|
// This is the null pointer reference bug. If you try to access
|
// something on the bus, at an address with no mapping, the bus
|
// something on the bus, at an address with no mapping, the bus
|
// should produce an error--such as if you try to access something
|
// should produce an error--such as if you try to access something
|
// at zero.
|
// at zero.
|
//
|
//
|
// 2. STB is true, and more than one device is selected
|
// 2. STB is true, and more than one device is selected
|
//
|
//
|
// (This can be turned off, if you design this file well. For
|
// (This can be turned off, if you design this file well. For
|
// this line to be true means you have a design flaw.)
|
// this line to be true means you have a design flaw.)
|
//
|
//
|
// 3. If more than one ACK is every true at any given time.
|
// 3. If more than one ACK is every true at any given time.
|
//
|
//
|
// This is a bug of bus usage, combined with a subtle flaw in the
|
// This is a bug of bus usage, combined with a subtle flaw in the
|
// WB pipeline definition. You can issue bus requests, one per
|
// WB pipeline definition. You can issue bus requests, one per
|
// clock, and if you cross device boundaries with your requests,
|
// clock, and if you cross device boundaries with your requests,
|
// you may have things come back out of order (not detected here)
|
// you may have things come back out of order (not detected here)
|
// or colliding on return (detected here). The solution to this
|
// or colliding on return (detected here). The solution to this
|
// problem is to make certain that any burst request does not cross
|
// problem is to make certain that any burst request does not cross
|
// device boundaries. This is a requirement of whoever (or
|
// device boundaries. This is a requirement of whoever (or
|
// whatever) drives the bus.
|
// whatever) drives the bus.
|
//
|
//
|
assign wb_err = ((wb_stb)&&(none_sel || many_sel)) || many_ack;
|
assign wb_err = ((wb_stb)&&(none_sel || many_sel)) || many_ack;
|
|
|
// Addresses ...
|
// Addresses ...
|
//
|
//
|
// dev_sel
|
// dev_sel
|
//
|
//
|
// The device select lines
|
// The device select lines
|
//
|
//
|
//
|
//
|
|
|
|
|
//
|
//
|
// The skipaddr bitfield below is our cheaters way of handling
|
// The skipaddr bitfield below is our cheaters way of handling
|
// device selection. We grab particular wires from the bus to do
|
// device selection. We grab particular wires from the bus to do
|
// this, and ignore all others. While this may lead to some
|
// this, and ignore all others. While this may lead to some
|
// surprising results for the CPU when it tries to access an
|
// surprising results for the CPU when it tries to access an
|
// inappropriate address, it also minimizes our logic while also
|
// inappropriate address, it also minimizes our logic while also
|
// placing every address at the right address. The only problem is
|
// placing every address at the right address. The only problem is
|
// ... devices will also be at some unexpected addresses, but ... this
|
// ... devices will also be at some unexpected addresses, but ... this
|
// is still within our spec.
|
// is still within our spec.
|
//
|
//
|
wire [3:0] skipaddr;
|
wire [3:0] skipaddr;
|
assign skipaddr = {
|
assign skipaddr = {
|
wb_addr[(LGFLASHSZ-2)], // Flash
|
wb_addr[(LGFLASHSZ-2)], // Flash
|
wb_addr[(LGMEMSZ-2)], // RAM
|
wb_addr[(LGMEMSZ-2)], // RAM
|
wb_addr[ 9], // SCOPE
|
wb_addr[ 9], // SCOPE
|
wb_addr[ 8] }; // I/O
|
wb_addr[ 8] }; // I/O
|
//
|
//
|
// This might not be the most efficient way in hardware, but it will
|
// This might not be the most efficient way in hardware, but it will
|
// work for our purposes here. There are two phantom bits for each
|
// work for our purposes here. There are two phantom bits for each
|
// of these ... bits that tell the CPU which byte within the word, and
|
// of these ... bits that tell the CPU which byte within the word, and
|
// another phantom bit because we allocated a minimum of two words to
|
// another phantom bit because we allocated a minimum of two words to
|
// every device.
|
// every device.
|
//
|
//
|
wire idle_n;
|
wire idle_n;
|
`ifdef ZERO_ON_IDLE
|
`ifdef ZERO_ON_IDLE
|
assign idle_n = wb_stb;
|
assign idle_n = wb_stb;
|
`else
|
`else
|
assign idle_n = 1'b1;
|
assign idle_n = 1'b1;
|
`endif
|
`endif
|
|
|
// `define ZERO_ON_IDLE
|
// `define ZERO_ON_IDLE
|
`ifdef ZERO_ON_IDLE
|
`ifdef ZERO_ON_IDLE
|
assign idle_n = (wb_cyc)&&(wb_stb);
|
assign idle_n = (wb_cyc)&&(wb_stb);
|
`else
|
`else
|
assign idle_n = 1'b1;
|
assign idle_n = 1'b1;
|
`endif
|
`endif
|
assign io_sel =((idle_n)&&(skipaddr[3:0]==4'h1));
|
assign io_sel =((idle_n)&&(skipaddr[3:0]==4'h1));
|
assign scop_sel =((idle_n)&&(skipaddr[3:1]==3'h1)); // = 4'h2
|
assign scop_sel =((idle_n)&&(skipaddr[3:1]==3'h1)); // = 4'h2
|
assign flctl_sel= 1'b0; // ((wb_cyc)&&(skipaddr[3:0]==4'h3));
|
assign flctl_sel= 1'b0; // ((wb_cyc)&&(skipaddr[3:0]==4'h3));
|
assign mem_sel =((idle_n)&&(skipaddr[3:2]==2'h1));
|
assign mem_sel =((idle_n)&&(skipaddr[3:2]==2'h1));
|
assign flash_sel=((idle_n)&&(skipaddr[3]));
|
assign flash_sel=((idle_n)&&(skipaddr[3]));
|
|
|
//
|
//
|
// none_sel
|
// none_sel
|
//
|
//
|
// This wire is true if wb_stb is true and no device is selected. This
|
// This wire is true if wb_stb is true and no device is selected. This
|
// is an error condition, but here we present the logic to test for it.
|
// is an error condition, but here we present the logic to test for it.
|
//
|
//
|
//
|
//
|
// If you add another device, add another OR into the select lines
|
// If you add another device, add another OR into the select lines
|
// associated with this term.
|
// associated with this term.
|
//
|
//
|
assign none_sel =((wb_stb)&&(skipaddr==4'h0));
|
assign none_sel =((wb_stb)&&(skipaddr==4'h0));
|
|
|
//
|
//
|
// many_sel
|
// many_sel
|
//
|
//
|
// This should *never* be true .... unless you mess up your address
|
// This should *never* be true .... unless you mess up your address
|
// decoding logic. Since I've done that before, I test/check for it
|
// decoding logic. Since I've done that before, I test/check for it
|
// here.
|
// here.
|
//
|
//
|
// To add a new device here, simply add it to the list. Make certain
|
// To add a new device here, simply add it to the list. Make certain
|
// that the width of the add, however, is greater than the number
|
// that the width of the add, however, is greater than the number
|
// of devices below. Hence, for 3 devices, you will need an add
|
// of devices below. Hence, for 3 devices, you will need an add
|
// at least 3 bits in width, for 7 devices you will need at least 4
|
// at least 3 bits in width, for 7 devices you will need at least 4
|
// bits, etc.
|
// bits, etc.
|
//
|
//
|
// Because this add uses the {} operator, the individual components to
|
// Because this add uses the {} operator, the individual components to
|
// it are by default unsigned ... just as we would like.
|
// it are by default unsigned ... just as we would like.
|
//
|
//
|
// There's probably another easier/better/faster/cheaper way to do this,
|
// There's probably another easier/better/faster/cheaper way to do this,
|
// but I haven't found any such that are also easier to adjust with
|
// but I haven't found any such that are also easier to adjust with
|
// new devices. I'm open to options.
|
// new devices. I'm open to options.
|
//
|
//
|
assign many_sel = 1'b0;
|
assign many_sel = 1'b0;
|
|
|
//
|
//
|
// many_ack
|
// many_ack
|
//
|
//
|
// Normally this would capture the error when multiple things creates acks
|
// Normally this would capture the error when multiple things creates acks
|
// at the same time. The S6 is small, though, and doesn't have the logic
|
// at the same time. The S6 is small, though, and doesn't have the logic
|
// we need to do this right. Hence we just declare (and hope) that this
|
// we need to do this right. Hence we just declare (and hope) that this
|
// will never be true and work with that.
|
// will never be true and work with that.
|
//
|
//
|
assign many_ack = 1'b0;
|
assign many_ack = 1'b0;
|
|
|
|
|
wire flash_interrupt, scop_interrupt, timer_int,
|
wire flash_interrupt, scop_interrupt, timer_int,
|
gpio_int, pwm_int, keypad_int,button_int;
|
gpio_int, pwm_int, keypad_int,button_int;
|
|
|
|
|
//
|
//
|
// bus_err_addr
|
// bus_err_addr
|
//
|
//
|
// We'd like to know, after the fact, what (if any) address caused a
|
// We'd like to know, after the fact, what (if any) address caused a
|
// bus error. So ... if we get a bus error, let's record the address
|
// bus error. So ... if we get a bus error, let's record the address
|
// on the bus for later analysis.
|
// on the bus for later analysis.
|
//
|
//
|
initial bus_err_addr = 0;
|
initial bus_err_addr = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wb_err)
|
if (wb_err)
|
bus_err_addr <= wb_addr;
|
bus_err_addr <= wb_addr;
|
//
|
//
|
// Interrupt processing
|
// Interrupt processing
|
//
|
//
|
// The interrupt controller will be used to tell us if any interrupts
|
// The interrupt controller will be used to tell us if any interrupts
|
// take place.
|
// take place.
|
//
|
//
|
// To add more interrupts, you can just add more wires to this
|
// To add more interrupts, you can just add more wires to this
|
// int_vector.
|
// int_vector.
|
//
|
//
|
reg rx_rdy;
|
reg rx_rdy;
|
wire [10:0] int_vector;
|
wire [10:0] int_vector;
|
assign int_vector = {
|
assign int_vector = {
|
gpio_int, pwm_int, keypad_int,
|
gpio_int, pwm_int, keypad_int,
|
(!tx_stb), rx_rdy,
|
(!tx_stb), rx_rdy,
|
1'b0, timer_int,
|
1'b0, timer_int,
|
1'b0, scop_interrupt,
|
1'b0, scop_interrupt,
|
wb_err, button_int };
|
wb_err, button_int };
|
|
|
wire [31:0] pic_data;
|
wire [31:0] pic_data;
|
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
|
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
|
&&(wb_addr[3:0]==4'h0)&&(wb_we),
|
&&(wb_addr[3:0]==4'h0)&&(wb_we),
|
wb_data, pic_data, int_vector, w_interrupt);
|
wb_data, pic_data, int_vector, w_interrupt);
|
|
|
wire [31:0] timer_data, watchdog_data;
|
wire [31:0] timer_data, watchdog_data;
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
ziptimer #(32,31,1)
|
ziptimer #(32,31,1)
|
thetimer(i_clk, 1'b0, 1'b1, wb_cyc,
|
thetimer(i_clk, 1'b0, 1'b1, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
wb_we, wb_data, zta_ack, zta_stall, timer_data,
|
wb_we, wb_data, zta_ack, zta_stall, timer_data,
|
timer_int);
|
timer_int);
|
ziptimer #(32,31,0)
|
ziptimer #(32,31,0)
|
watchdog(i_clk, cpu_reset, 1'b1, wb_cyc,
|
watchdog(i_clk, cpu_reset, 1'b1, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
wb_we, wb_data, ztb_ack, ztb_stall, watchdog_data,
|
wb_we, wb_data, ztb_ack, ztb_stall, watchdog_data,
|
watchdog_int);
|
watchdog_int);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
case(wb_addr[3:0])
|
case(wb_addr[3:0])
|
4'h0: io_data <= pic_data;
|
4'h0: io_data <= pic_data;
|
4'h1: io_data <= { {(30-BAW){1'b0}}, bus_err_addr, 2'b00 };
|
4'h1: io_data <= { {(30-BAW){1'b0}}, bus_err_addr, 2'b00 };
|
4'h2: io_data <= timer_data;
|
4'h2: io_data <= timer_data;
|
4'h3: io_data <= watchdog_data;
|
4'h3: io_data <= watchdog_data;
|
4'h4: io_data <= pwm_data;
|
4'h4: io_data <= pwm_data;
|
4'h5: io_data <= spio_data;
|
4'h5: io_data <= spio_data;
|
4'h6: io_data <= gpio_data;
|
4'h6: io_data <= gpio_data;
|
4'h7: io_data <= uart_data;
|
4'h7: io_data <= uart_data;
|
default: io_data <= `DATESTAMP;
|
default: io_data <= `DATESTAMP;
|
// 4'h8: io_data <= `DATESTAMP;
|
// 4'h8: io_data <= `DATESTAMP;
|
endcase
|
endcase
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
io_ack <= (wb_stb)&&(io_sel);
|
io_ack <= (wb_stb)&&(io_sel);
|
assign io_stall = 1'b0;
|
assign io_stall = 1'b0;
|
|
|
wire pwm_ack, pwm_stall;
|
wire pwm_ack, pwm_stall;
|
wbpwmaudio #(14'd10000,2,0,14)
|
wbpwmaudio #(14'd10000,2,0,14)
|
theaudio(i_clk, wb_cyc,
|
theaudio(i_clk, wb_cyc,
|
((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
|
((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
|
wb_we, 1'b0, wb_data,
|
wb_we, 1'b0, wb_data,
|
pwm_ack, pwm_stall, pwm_data, o_pwm,
|
pwm_ack, pwm_stall, pwm_data, o_pwm,
|
o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
|
o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
|
pwm_int);
|
pwm_int);
|
|
|
//
|
//
|
// Special Purpose I/O: Keypad, button, LED status and control
|
// Special Purpose I/O: Keypad, button, LED status and control
|
//
|
//
|
wire [3:0] w_led;
|
wire [3:0] w_led;
|
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),
|
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),
|
wb_we, wb_data, spio_data,
|
wb_we, wb_data, spio_data,
|
o_kp_col, i_kp_row, i_btn, w_led,
|
o_kp_col, i_kp_row, i_btn, w_led,
|
keypad_int, button_int);
|
keypad_int, button_int);
|
assign o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,w_led[1:0] };
|
assign o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,
|
|
w_led[1], w_led[0] };
|
|
|
//
|
//
|
// General purpose (sort of) I/O: (Bottom two bits robbed in each
|
// General purpose (sort of) I/O: (Bottom two bits robbed in each
|
// direction for an I2C link at the toplevel.v design)
|
// direction for an I2C link at the toplevel.v design)
|
//
|
//
|
wbgpio #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
|
wbgpio #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
|
wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
|
wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
|
|
|
//
|
//
|
//
|
//
|
// UART device: our console
|
// UART device: our console
|
//
|
//
|
//
|
//
|
wire [30:0] uart_setup;
|
wire [30:0] uart_setup;
|
//
|
//
|
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, rx_stb;
|
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, rx_stb;
|
wire [7:0] rx_data;
|
wire [7:0] rx_data;
|
//
|
//
|
assign uart_setup = UART_SETUP;
|
assign uart_setup = UART_SETUP;
|
//
|
//
|
|
`ifdef HAS_RXUART
|
|
`ifdef USE_LITE_UART
|
|
rxuartlite #(UART_SETUP[23:0])
|
|
rcvuart(i_clk, i_uart, rx_stb, rx_data);
|
|
assign rx_break = 1'b0;
|
|
assign rx_parity_err = 1'b0;
|
|
assign rx_frame_err = 1'b0;
|
|
assign rx_ck_uart = 1'b0;
|
|
`else
|
rxuart #(UART_SETUP)
|
rxuart #(UART_SETUP)
|
rcvuart(i_clk, 1'b0, uart_setup, i_uart, rx_stb, rx_data,
|
rcvuart(i_clk, 1'b0, uart_setup, i_uart, rx_stb, rx_data,
|
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
|
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
|
|
`endif
|
|
`else
|
|
assign rx_break = 1'b0;
|
|
assign rx_parity_err = 1'b0;
|
|
assign rx_frame_err = 1'b0;
|
|
assign rx_ck_uart = 1'b0;
|
|
assign rx_stb = 1'b0;
|
|
assign rx_data = 8'h0;
|
|
`endif
|
//
|
//
|
wire tx_break, tx_busy;
|
wire tx_break, tx_busy;
|
reg tx_stb;
|
reg tx_stb;
|
reg [7:0] tx_data;
|
reg [7:0] tx_data;
|
assign tx_break = 1'b0;
|
assign tx_break = 1'b0;
|
|
`ifdef USE_LITE_UART
|
|
txuartlite #(UART_SETUP[23:0])
|
|
tcvuart(i_clk, tx_stb, tx_data, o_uart, tx_busy);
|
|
`else
|
txuart #(UART_SETUP)
|
txuart #(UART_SETUP)
|
tcvuart(i_clk, 1'b0, uart_setup, tx_break, tx_stb, tx_data,
|
tcvuart(i_clk, 1'b0, uart_setup, tx_break, tx_stb, tx_data,
|
i_uart_cts_n, o_uart, tx_busy);
|
i_uart_cts_n, o_uart, tx_busy);
|
|
`endif
|
|
|
//
|
//
|
// Rudimentary serial port control
|
// Rudimentary serial port control
|
//
|
//
|
reg [7:0] r_rx_data;
|
reg [7:0] r_rx_data;
|
// Baud rate is set by clock rate / baud rate.
|
// Baud rate is set by clock rate / baud rate.
|
|
|
initial tx_stb = 1'b0;
|
initial tx_stb = 1'b0;
|
initial tx_data = 8'h00;
|
initial tx_data = 8'h00;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
|
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
|
begin
|
begin
|
tx_data <= wb_data[7:0];
|
tx_data <= wb_data[7:0];
|
tx_stb <= 1'b1;
|
tx_stb <= 1'b1;
|
end
|
end
|
else if ((tx_stb)&&(!tx_busy))
|
else if ((tx_stb)&&(!tx_busy))
|
tx_stb <= 1'b0;
|
tx_stb <= 1'b0;
|
|
`ifdef HAS_RXUART
|
initial rx_rdy = 1'b0;
|
initial rx_rdy = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (rx_stb)
|
if (rx_stb)
|
r_rx_data <= rx_data;
|
r_rx_data <= rx_data;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(!wb_we))
|
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(!wb_we))
|
rx_rdy <= rx_stb;
|
rx_rdy <= rx_stb;
|
else if (rx_stb)
|
else
|
rx_rdy <= (rx_rdy | rx_stb);
|
rx_rdy <= (rx_rdy | rx_stb);
|
end
|
end
|
assign o_uart_rts_n = (rx_rdy);
|
assign o_uart_rts_n = (rx_rdy);
|
assign uart_data = { 23'h0, !rx_rdy, r_rx_data };
|
assign uart_data = { 23'h0, !rx_rdy, r_rx_data };
|
|
`else
|
|
assign o_uart_rts_n = 1'b1;
|
|
assign uart_data = 32'h00;
|
|
`endif
|
//
|
//
|
// uart_ack gets returned as part of io_ack, since that happens when
|
// uart_ack gets returned as part of io_ack, since that happens when
|
// io_sel and wb_stb are defined
|
// io_sel and wb_stb are defined
|
//
|
//
|
// always @(posedge i_clk)
|
// always @(posedge i_clk)
|
// uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
|
// uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
|
|
|
|
|
|
|
//
|
//
|
// FLASH MEMORY CONFIGURATION ACCESS
|
// FLASH MEMORY CONFIGURATION ACCESS
|
//
|
//
|
`ifdef FLASH_ACCESS
|
`ifdef FLASH_ACCESS
|
|
`ifdef LOWLOGIC_FLASH
|
|
qflashxpress flashmem(i_clk,
|
|
wb_cyc,(wb_stb)&&(flash_sel),
|
|
wb_addr[(LGFLASHSZ-3):0],
|
|
flash_ack, flash_stall, flash_data,
|
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat);
|
|
|
|
assign flash_interrupt = 1'b0;
|
|
`else
|
wbqspiflash #(LGFLASHSZ) flashmem(i_clk,
|
wbqspiflash #(LGFLASHSZ) flashmem(i_clk,
|
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_addr[(LGFLASHSZ-3):0], wb_data,
|
wb_addr[(LGFLASHSZ-3):0], wb_data,
|
flash_ack, flash_stall, flash_data,
|
flash_ack, flash_stall, flash_data,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
flash_interrupt);
|
flash_interrupt);
|
|
`endif
|
`else
|
`else
|
reg r_flash_ack;
|
reg r_flash_ack;
|
initial r_flash_ack = 1'b0;
|
initial r_flash_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
|
r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
|
|
|
assign flash_ack = r_flash_ack;
|
assign flash_ack = r_flash_ack;
|
assign flash_stall = 1'b0;
|
assign flash_stall = 1'b0;
|
assign flash_data = 32'h0000;
|
assign flash_data = 32'h0000;
|
assign flash_interrupt = 1'b0;
|
assign flash_interrupt = 1'b0;
|
|
|
assign o_qspi_sck = 1'b1;
|
assign o_qspi_sck = 1'b1;
|
assign o_qspi_cs_n = 1'b1;
|
assign o_qspi_cs_n = 1'b1;
|
assign o_qspi_mod = 2'b01;
|
assign o_qspi_mod = 2'b01;
|
assign o_qspi_dat = 4'b1111;
|
assign o_qspi_dat = 4'b1111;
|
`endif
|
`endif
|
|
|
//
|
//
|
// ON-CHIP RAM MEMORY ACCESS
|
// ON-CHIP RAM MEMORY ACCESS
|
//
|
//
|
`ifdef IMPLEMENT_ONCHIP_RAM
|
`ifdef IMPLEMENT_ONCHIP_RAM
|
memdev #(.LGMEMSZ(LGMEMSZ))
|
memdev #(.LGMEMSZ(LGMEMSZ))
|
ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
wb_addr[(LGMEMSZ-3):0], wb_data, wb_sel,
|
wb_addr[(LGMEMSZ-3):0], wb_data, wb_sel,
|
mem_ack, mem_stall, mem_data);
|
mem_ack, mem_stall, mem_data);
|
`else
|
`else
|
assign mem_data = 32'h00;
|
assign mem_data = 32'h00;
|
assign mem_stall = 1'b0;
|
assign mem_stall = 1'b0;
|
reg r_mem_ack;
|
reg r_mem_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_mem_ack <= (wb_stb)&&(mem_sel);
|
r_mem_ack <= (wb_stb)&&(mem_sel);
|
assign mem_ack = r_mem_ack;
|
assign mem_ack = r_mem_ack;
|
`endif
|
`endif
|
|
|
//
|
//
|
//
|
//
|
// WISHBONE SCOPE
|
// WISHBONE SCOPE
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
wire [31:0] scop_cpu_data;
|
wire [31:0] scop_cpu_data;
|
wire scop_cpu_ack, scop_cpu_stall, scop_cpu_interrupt;
|
wire scop_cpu_ack, scop_cpu_stall, scop_cpu_interrupt;
|
`ifdef DBG_SCOPE
|
`ifdef DBG_SCOPE
|
wire scop_trigger = (zip_cpu_int) || (cpu_reset);
|
wire scop_trigger = (zip_cpu_int) || (cpu_reset);
|
`ifdef COMPRESSED_SCOPE
|
`ifdef COMPRESSED_SCOPE
|
wbscopc #(5'ha)
|
wbscopc #(5'ha)
|
`else
|
`else
|
wbscope #(.LGMEM(5'h6), .HOLDOFFBITS(9))
|
wbscope #(.LGMEM(5'h6), .HOLDOFFBITS(9))
|
`endif
|
`endif
|
cpuscope(i_clk, 1'b1, scop_trigger,
|
cpuscope(i_clk, 1'b1, scop_trigger,
|
`ifdef COMPRESSED_SCOPE
|
`ifdef COMPRESSED_SCOPE
|
// cfg_scope[30:0],
|
// cfg_scope[30:0],
|
zip_scope_data[30:0],
|
zip_scope_data[30:0],
|
`else
|
`else
|
// cfg_scope[31:0],
|
// cfg_scope[31:0],
|
zip_scope_data[31:0],
|
zip_scope_data[31:0],
|
`endif
|
`endif
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
|
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
|
scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
|
scop_cpu_interrupt);
|
scop_cpu_interrupt);
|
`else
|
`else
|
reg r_scop_cpu_ack;
|
reg r_scop_cpu_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_scop_cpu_ack <= (wb_stb)&&(scop_sel);
|
r_scop_cpu_ack <= (wb_stb)&&(scop_sel);
|
assign scop_cpu_ack = r_scop_cpu_ack;
|
assign scop_cpu_ack = r_scop_cpu_ack;
|
assign scop_cpu_data = 32'h000;
|
assign scop_cpu_data = 32'h000;
|
assign scop_cpu_stall= 1'b0;
|
assign scop_cpu_stall= 1'b0;
|
`endif
|
`endif
|
|
|
assign scop_interrupt = scop_cpu_interrupt;
|
assign scop_interrupt = scop_cpu_interrupt;
|
assign scop_ack = scop_cpu_ack;
|
assign scop_ack = scop_cpu_ack;
|
assign scop_stall = scop_cpu_stall;
|
assign scop_stall = scop_cpu_stall;
|
assign scop_data = scop_cpu_data;
|
assign scop_data = scop_cpu_data;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
