| Line 42... |
Line 42... |
`define IMPLEMENT_ONCHIP_RAM // 2804 w/o after synthesis
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`define IMPLEMENT_ONCHIP_RAM // 2804 w/o after synthesis
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`ifndef VERILATOR
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`ifndef VERILATOR
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`define FANCY_ICAP_ACCESS
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`define FANCY_ICAP_ACCESS
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`endif
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`endif
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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// `define CFG_SCOPE // About 204 LUTs, at 2^6 addresses
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`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
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`define INCLUDE_RTC // About 90 LUTs
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// `define INCLUDE_RTC // About 90 LUTs
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module busmaster(i_clk, i_rst,
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module busmaster(i_clk, i_rst,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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o_uart_rts,
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o_uart_rts,
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// The SPI Flash lines
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// The SPI Flash lines
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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| Line 288... |
Line 288... |
always @(posedge i_clk)
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always @(posedge i_clk)
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r_rtc_ack <= ((wb_stb)&&(rtc_sel));
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r_rtc_ack <= ((wb_stb)&&(rtc_sel));
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assign rtc_ack = r_rtc_ack;
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assign rtc_ack = r_rtc_ack;
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|
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rtclight
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rtclight
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#(32'h35afe5,23) // 80 MHz clock
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#(32'h35afe5,23,0,0) // 80 MHz clock
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thetime(i_clk, wb_cyc,
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thetime(i_clk, wb_cyc,
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((wb_stb)&&(rtc_sel)), wb_we,
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((wb_stb)&&(rtc_sel)), wb_we,
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{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
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{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
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rtc_interrupt, ppd);
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rtc_interrupt, ppd);
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`else
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`else
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| Line 350... |
Line 350... |
// = 694.4, or about 0x2b6.
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// = 694.4, or about 0x2b6.
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// although the CPU might struggle to keep up at this speed without a
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// although the CPU might struggle to keep up at this speed without a
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// hardware buffer.
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// hardware buffer.
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//
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//
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// We'll add the flag for two stop bits.
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// We'll add the flag for two stop bits.
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assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
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// assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
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assign o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
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|
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initial o_tx_stb = 1'b0;
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initial o_tx_stb = 1'b0;
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initial o_tx_data = 8'h00;
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initial o_tx_data = 8'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
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if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
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| Line 439... |
Line 440... |
//
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//
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//
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//
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//
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//
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wire [31:0] scop_cfg_data;
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wire [31:0] scop_cfg_data;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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`ifdef CFG_SCOPE
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`ifdef DBG_SCOPE
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wire scop_cfg_trigger;
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wire scop_cfg_trigger;
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assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
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assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
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wbscope #(5'h6) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
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wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
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// Wishbone interface
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// Wishbone interface
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i_clk, wb_cyc, (wb_stb)&&(scop_sel),
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i_clk, wb_cyc, (wb_stb)&&(scop_sel),
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wb_we, wb_addr[0], wb_data,
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wb_we, wb_addr[0], wb_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_cfg_interrupt);
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scop_cfg_interrupt);
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