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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: cpuops.v
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// Filename: cpuops.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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`include "cpudefs.v"
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//
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//
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`define LONG_MPY
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module cpuops(i_clk,i_rst, i_ce, i_op, i_a, i_b, o_c, o_f, o_valid,
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module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
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o_busy);
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o_illegal, o_busy);
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parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
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parameter IMPLEMENT_MPY = 1;
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input i_clk, i_rst, i_ce;
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input i_clk, i_rst, i_ce;
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input [3:0] i_op;
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input [3:0] i_op;
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input [31:0] i_a, i_b;
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input [31:0] i_a, i_b;
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input i_valid;
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output reg [31:0] o_c;
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output reg [31:0] o_c;
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output wire [3:0] o_f;
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output wire [3:0] o_f;
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output reg o_valid;
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output reg o_valid;
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output wire o_illegal;
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output wire o_busy;
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output wire o_busy;
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// Rotate-left pre-logic
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wire [63:0] w_rol_tmp;
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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wire [31:0] w_rol_result;
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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// Shift register pre-logic
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// Shift register pre-logic
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wire [32:0] w_lsr_result, w_asr_result;
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wire [32:0] w_lsr_result, w_asr_result, w_lsl_result;
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wire signed [32:0] w_pre_asr_input, w_pre_asr_shifted;
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assign w_pre_asr_input = { i_a, 1'b0 };
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assign w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
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: w_pre_asr_shifted;// ASR
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assign w_lsr_result = (|i_b[31:5])? 33'h00
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assign w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
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: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
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:((i_b[5])?{32'h0,i_a[31]}
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: ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR
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assign w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
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:((i_b[5])?{i_a[0], 32'h0}
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: ({1'b0, i_a } << i_b[4:0])); // LSL
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// Bit reversal pre-logic
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// Bit reversal pre-logic
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wire [31:0] w_brev_result;
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wire [31:0] w_brev_result;
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genvar k;
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genvar k;
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generate
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generate
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for(k=0; k<32; k=k+1)
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for(k=0; k<32; k=k+1)
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begin : bit_reversal_cpuop
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begin : bit_reversal_cpuop
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assign w_brev_result[k] = i_b[31-k];
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assign w_brev_result[k] = i_b[31-k];
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end endgenerate
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end endgenerate
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// Popcount pre-logic
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wire [31:0] w_popc_result;
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assign w_popc_result[5:0]=
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({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
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+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})
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+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})
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+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})
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+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})
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+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})
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+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})
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+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});
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assign w_popc_result[31:6] = 26'h00;
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// Prelogic for our flags registers
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// Prelogic for our flags registers
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wire z, n, v;
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wire z, n, v;
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reg c, pre_sign, set_ovfl;
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reg c, pre_sign, set_ovfl, keep_sgn_on_ovfl;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce) // 1 LUT
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if (i_ce) // 1 LUT
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set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
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||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
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||(i_op == 4'h6) // LSL
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||(i_op == 4'h6) // LSL
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||(i_op == 4'h5)); // LSR
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||(i_op == 4'h5)); // LSR
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always @(posedge i_clk)
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`ifdef LONG_MPY
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if (i_ce) // 1 LUT
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reg mpyhi;
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keep_sgn_on_ovfl<=
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wire mpybusy;
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(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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`endif
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||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD
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wire [63:0] mpy_result; // Where we dump the multiply result
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reg mpyhi; // Return the high half of the multiply
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wire mpybusy; // The multiply is busy if true
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wire mpydone; // True if we'll be valid on the next clock;
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// A 4-way multiplexer can be done in one 6-LUT.
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// A 4-way multiplexer can be done in one 6-LUT.
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// the Xilinx multiplexer fabric that follows.
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// the Xilinx multiplexer fabric that follows.
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// Given that we wish to apply this multiplexer approach to 33-bits,
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// Given that we wish to apply this multiplexer approach to 33-bits,
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// this will cost a minimum of 132 6-LUTs.
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// this will cost a minimum of 132 6-LUTs.
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wire this_is_a_multiply_op;
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assign this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc));
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generate
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generate
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if (IMPLEMENT_MPY == 0)
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if (IMPLEMENT_MPY == 0)
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begin
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begin // No multiply support.
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assign mpy_result = 63'h00;
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end else if (IMPLEMENT_MPY == 1)
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begin // Our single clock option (no extra clocks)
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wire signed [63:0] w_mpy_a_input, w_mpy_b_input;
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assign w_mpy_a_input = {{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
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assign w_mpy_b_input = {{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
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assign mpy_result = w_mpy_a_input * w_mpy_b_input;
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assign mpybusy = 1'b0;
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assign mpydone = 1'b0;
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always @(*) mpyhi = 1'b0; // Not needed
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end else if (IMPLEMENT_MPY == 2)
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begin // Our two clock option (ALU must pause for 1 clock)
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reg signed [63:0] r_mpy_a_input, r_mpy_b_input;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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begin
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begin
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pre_sign <= (i_a[31]);
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r_mpy_a_input <={{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
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c <= 1'b0;
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r_mpy_b_input <={{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
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casez(i_op)
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4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
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4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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`ifndef LONG_MPY
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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`endif
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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// 4'h1010: The unimplemented MPYU,
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// 4'h1011: and here for the unimplemented MPYS
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1110: o_c <= w_rol_result; // ROL
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default: o_c <= i_b; // MOV, LDI
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endcase
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end
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end
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assign o_busy = 1'b0;
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assign mpy_result = r_mpy_a_input * r_mpy_b_input;
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assign mpybusy = 1'b0;
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reg r_illegal;
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always @(posedge i_clk)
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r_illegal <= (i_ce)&&((i_op == 4'ha)||(i_op == 4'hb)
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`ifdef LONG_MPY
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||(i_op == 4'h8)
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`endif
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);
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assign o_illegal = r_illegal;
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end else begin
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//
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// Multiply pre-logic
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//
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`ifdef LONG_MPY
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reg [63:0] r_mpy_result;
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if (IMPLEMENT_MPY == 1)
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begin // Our two clock option (one clock extra)
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reg signed [64:0] r_mpy_a_input, r_mpy_b_input;
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reg mpypipe, x;
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initial mpypipe = 1'b0;
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initial mpypipe = 1'b0;
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reg mpypipe;
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always @(posedge i_clk)
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always @(posedge i_clk)
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mpypipe <= (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'h8));
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if (i_rst)
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mpypipe <= 1'b0;
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else
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mpypipe <= (this_is_a_multiply_op);
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assign mpydone = mpypipe; // this_is_a_multiply_op;
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always @(posedge i_clk)
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if (this_is_a_multiply_op)
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mpyhi = i_op[1];
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end else if (IMPLEMENT_MPY == 3)
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begin // Our three clock option (ALU pauses for 2 clocks)
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reg signed [63:0] r_smpy_result;
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reg [63:0] r_umpy_result;
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reg signed [31:0] r_mpy_a_input, r_mpy_b_input;
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reg [1:0] mpypipe;
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reg [1:0] r_sgn;
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initial mpypipe = 2'b0;
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always @(posedge i_clk)
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if (i_rst)
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mpypipe <= 2'b0;
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else
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mpypipe <= { mpypipe[0], this_is_a_multiply_op };
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// First clock
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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begin
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begin
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r_mpy_a_input <= {{(33){(i_a[31])&(i_op[0])}},
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r_mpy_a_input <= i_a[31:0];
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i_a[31:0]};
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r_mpy_b_input <= i_b[31:0];
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r_mpy_b_input <= {{(33){(i_b[31])&(i_op[0])}},
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r_sgn <= { r_sgn[0], i_op[0] };
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i_b[31:0]};
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end
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end
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// Second clock
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`ifdef VERILATOR
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wire signed [63:0] s_mpy_a_input, s_mpy_b_input;
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wire [63:0] u_mpy_a_input, u_mpy_b_input;
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|
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assign s_mpy_a_input = {{(32){r_mpy_a_input[31]}},r_mpy_a_input};
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assign s_mpy_b_input = {{(32){r_mpy_b_input[31]}},r_mpy_b_input};
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assign u_mpy_a_input = {32'h00,r_mpy_a_input};
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assign u_mpy_b_input = {32'h00,r_mpy_b_input};
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (mpypipe)
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r_smpy_result = s_mpy_a_input * s_mpy_b_input;
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{x, r_mpy_result} = r_mpy_a_input
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* r_mpy_b_input;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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r_umpy_result = u_mpy_a_input * u_mpy_b_input;
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`else
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|
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wire [31:0] u_mpy_a_input, u_mpy_b_input;
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|
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assign u_mpy_a_input = r_mpy_a_input;
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assign u_mpy_b_input = r_mpy_b_input;
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always @(posedge i_clk)
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r_smpy_result = r_mpy_a_input * r_mpy_b_input;
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always @(posedge i_clk)
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r_umpy_result = u_mpy_a_input * u_mpy_b_input;
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`endif
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always @(posedge i_clk)
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if (this_is_a_multiply_op)
|
mpyhi = i_op[1];
|
mpyhi = i_op[1];
|
assign mpybusy = mpypipe;
|
assign mpybusy = mpypipe[0];
|
end else if (IMPLEMENT_MPY == 2)
|
assign mpy_result = (r_sgn[1])?r_smpy_result:r_umpy_result;
|
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assign mpydone = mpypipe[1];
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|
|
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// Results are then set on the third clock
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|
end else // if (IMPLEMENT_MPY <= 4)
|
begin // The three clock option
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begin // The three clock option
|
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reg [63:0] r_mpy_result;
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reg [31:0] r_mpy_a_input, r_mpy_b_input;
|
reg [31:0] r_mpy_a_input, r_mpy_b_input;
|
reg r_mpy_signed;
|
reg r_mpy_signed;
|
reg [1:0] mpypipe;
|
reg [2:0] mpypipe;
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|
|
// First clock, latch in the inputs
|
// First clock, latch in the inputs
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
// mpypipe indicates we have a multiply in the
|
// mpypipe indicates we have a multiply in the
|
// pipeline. In this case, the multiply
|
// pipeline. In this case, the multiply
|
// pipeline is a two stage pipeline, so we need
|
// pipeline is a two stage pipeline, so we need
|
// two bits in the pipe.
|
// two bits in the pipe.
|
mpypipe[0] <= (i_ce)&&((i_op[3:1]==3'h5)
|
if (i_rst)
|
||(i_op[3:0]==4'h8));
|
mpypipe <= 3'h0;
|
|
else begin
|
|
mpypipe[0] <= this_is_a_multiply_op;
|
mpypipe[1] <= mpypipe[0];
|
mpypipe[1] <= mpypipe[0];
|
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mpypipe[2] <= mpypipe[1];
|
|
end
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|
|
if (i_op[0]) // i.e. if signed multiply
|
if (i_op[0]) // i.e. if signed multiply
|
begin
|
begin
|
r_mpy_a_input <= {(~i_a[31]),i_a[30:0]};
|
r_mpy_a_input <= {(~i_a[31]),i_a[30:0]};
|
r_mpy_b_input <= {(~i_b[31]),i_b[30:0]};
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r_mpy_b_input <= {(~i_b[31]),i_b[30:0]};
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| Line 199... |
Line 231... |
// case of 64 bit multiply. We'll keep track
|
// case of 64 bit multiply. We'll keep track
|
// of it, though, and pretend in all other
|
// of it, though, and pretend in all other
|
// cases.
|
// cases.
|
r_mpy_signed <= i_op[0];
|
r_mpy_signed <= i_op[0];
|
|
|
if (i_ce)
|
if (this_is_a_multiply_op)
|
mpyhi = i_op[1];
|
mpyhi = i_op[1];
|
end
|
end
|
|
|
assign mpybusy = |mpypipe;
|
assign mpybusy = |mpypipe[1:0];
|
|
assign mpydone = mpypipe[2];
|
|
|
// Second clock, do the multiplies, get the "partial
|
// Second clock, do the multiplies, get the "partial
|
// products". Here, we break our input up into two
|
// products". Here, we break our input up into two
|
// halves,
|
// halves,
|
//
|
//
|
| Line 266... |
Line 299... |
{ 32'h00, pp_l[31:16] }
|
{ 32'h00, pp_l[31:16] }
|
+ { 15'h00, pp_oi }
|
+ { 15'h00, pp_oi }
|
+ { pp_s, 15'h00 }
|
+ { pp_s, 15'h00 }
|
+ { pp_f, 16'h00 };
|
+ { pp_f, 16'h00 };
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end
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end
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end // Fourth clock -- results are available for writeback.
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`else
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assign mpy_result = r_mpy_result;
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wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
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// Fourth clock -- results are clocked into writeback
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wire [33:0] w_mpy_result;
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end
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reg [31:0] r_mpy_result;
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endgenerate // All possible multiply results have been determined
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assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
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assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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always @(posedge i_clk)
|
|
if (i_ce)
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|
r_mpy_result = w_mpy_result[31:0];
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`endif
|
|
|
|
//
|
//
|
// The master ALU case statement
|
// The master ALU case statement
|
//
|
//
|
always @(posedge i_clk)
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always @(posedge i_clk)
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| Line 294... |
Line 320... |
4'b0001: o_c <= i_a & i_b; // BTST/And
|
4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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`ifdef LONG_MPY
|
4'b1000: o_c <= w_brev_result; // BREV
|
4'b1000: o_c <= r_mpy_result[31:0]; // MPY
|
|
`else
|
|
4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
|
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`endif
|
|
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
|
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
|
`ifdef LONG_MPY
|
4'b1010: o_c <= mpy_result[63:32]; // MPYHU
|
4'b1010: o_c <= r_mpy_result[63:32]; // MPYHU
|
4'b1011: o_c <= mpy_result[63:32]; // MPYHS
|
4'b1011: o_c <= r_mpy_result[63:32]; // MPYHS
|
4'b1100: o_c <= mpy_result[31:0]; // MPY
|
`else
|
|
4'b1010: o_c <= r_mpy_result; // MPYU
|
|
4'b1011: o_c <= r_mpy_result; // MPYS
|
|
`endif
|
|
4'b1100: o_c <= w_brev_result; // BREV
|
|
4'b1101: o_c <= w_popc_result; // POPC
|
|
4'b1110: o_c <= w_rol_result; // ROL
|
|
default: o_c <= i_b; // MOV, LDI
|
default: o_c <= i_b; // MOV, LDI
|
endcase
|
endcase
|
end else if (r_busy)
|
end else // if (mpydone)
|
`ifdef LONG_MPY
|
o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];
|
o_c <= (mpyhi)?r_mpy_result[63:32]:r_mpy_result[31:0];
|
|
`else
|
|
o_c <= r_mpy_result;
|
|
`endif
|
|
|
|
reg r_busy;
|
reg r_busy;
|
initial r_busy = 1'b0;
|
initial r_busy = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
|
if (i_rst)
|
`ifdef LONG_MPY
|
r_busy <= 1'b0;
|
&&((i_op[3:1] == 3'h5)
|
else
|
||(i_op[3:0] == 4'h8))||mpybusy;
|
r_busy <= ((IMPLEMENT_MPY > 1)
|
`else
|
&&(this_is_a_multiply_op))||mpybusy;
|
&&(i_op[3:1] == 3'h5);
|
assign o_busy = (r_busy); // ||((IMPLEMENT_MPY>1)&&(this_is_a_multiply_op));
|
`endif
|
|
|
|
assign o_busy = r_busy;
|
|
|
|
assign o_illegal = 1'b0;
|
|
end endgenerate
|
|
|
|
assign z = (o_c == 32'h0000);
|
assign z = (o_c == 32'h0000);
|
assign n = (o_c[31]);
|
assign n = (o_c[31]);
|
assign v = (set_ovfl)&&(pre_sign != o_c[31]);
|
assign v = (set_ovfl)&&(pre_sign != o_c[31]);
|
|
wire vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]);
|
|
|
assign o_f = { v, n, c, z };
|
assign o_f = { v, n^vx, c, z };
|
|
|
initial o_valid = 1'b0;
|
initial o_valid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
o_valid <= 1'b0;
|
o_valid <= 1'b0;
|
|
else if (IMPLEMENT_MPY <= 1)
|
|
o_valid <= (i_ce);
|
else
|
else
|
o_valid <= (i_ce)&&(i_valid)
|
o_valid <=((i_ce)&&(!this_is_a_multiply_op))||(mpydone);
|
`ifdef LONG_MPY
|
|
&&(i_op[3:1] != 3'h5)&&(i_op[3:0] != 4'h8)
|
|
||(o_busy)&&(~mpybusy);
|
|
`else
|
|
&&(i_op[3:1] != 3'h5)||(o_busy);
|
|
`endif
|
|
endmodule
|
endmodule
|
|
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No newline at end of file
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No newline at end of file
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