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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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`define LONG_MPY
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module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
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module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
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o_illegal, o_busy);
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o_illegal, o_busy);
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parameter IMPLEMENT_MPY = 1;
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parameter IMPLEMENT_MPY = 1;
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input i_clk, i_rst, i_ce;
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input i_clk, i_rst, i_ce;
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input [3:0] i_op;
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input [3:0] i_op;
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| Line 88... |
Line 89... |
set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
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||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
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||(i_op == 4'h6) // LSL
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||(i_op == 4'h6) // LSL
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||(i_op == 4'h5)); // LSR
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||(i_op == 4'h5)); // LSR
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`ifdef LONG_MPY
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reg mpyhi;
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wire mpybusy;
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`endif
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// A 4-way multiplexer can be done in one 6-LUT.
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// A 4-way multiplexer can be done in one 6-LUT.
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// the Xilinx multiplexer fabric that follows.
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// the Xilinx multiplexer fabric that follows.
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// Given that we wish to apply this multiplexer approach to 33-bits,
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// Given that we wish to apply this multiplexer approach to 33-bits,
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| Line 111... |
Line 116... |
4'b0011: o_c <= i_a | i_b; // Or
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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`ifndef LONG_MPY
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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`endif
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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// 4'h1010: The unimplemented MPYU,
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// 4'h1010: The unimplemented MPYU,
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// 4'h1011: and here for the unimplemented MPYS
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// 4'h1011: and here for the unimplemented MPYS
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1101: o_c <= w_popc_result; // POPC
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| Line 126... |
Line 133... |
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assign o_busy = 1'b0;
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assign o_busy = 1'b0;
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reg r_illegal;
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reg r_illegal;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
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r_illegal <= (i_ce)&&((i_op == 4'ha)||(i_op == 4'hb)
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`ifdef LONG_MPY
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||(i_op == 4'h8)
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`endif
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);
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assign o_illegal = r_illegal;
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assign o_illegal = r_illegal;
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end else begin
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end else begin
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//
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//
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// Multiply pre-logic
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// Multiply pre-logic
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//
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//
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`ifdef LONG_MPY
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reg [63:0] r_mpy_result;
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if (IMPLEMENT_MPY == 1)
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begin // Our two clock option (one clock extra)
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reg signed [64:0] r_mpy_a_input, r_mpy_b_input;
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reg mpypipe, x;
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initial mpypipe = 1'b0;
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always @(posedge i_clk)
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mpypipe <= (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'h8));
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always @(posedge i_clk)
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if (i_ce)
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begin
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r_mpy_a_input <= {{(33){(i_a[31])&(i_op[0])}},
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i_a[31:0]};
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r_mpy_b_input <= {{(33){(i_b[31])&(i_op[0])}},
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i_b[31:0]};
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end
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always @(posedge i_clk)
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if (mpypipe)
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{x, r_mpy_result} = r_mpy_a_input
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* r_mpy_b_input;
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always @(posedge i_clk)
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if (i_ce)
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mpyhi = i_op[1];
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assign mpybusy = mpypipe;
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end else if (IMPLEMENT_MPY == 2)
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begin // The three clock option
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reg [31:0] r_mpy_a_input, r_mpy_b_input;
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reg r_mpy_signed;
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reg [1:0] mpypipe;
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// First clock, latch in the inputs
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always @(posedge i_clk)
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begin
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// mpypipe indicates we have a multiply in the
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// pipeline. In this case, the multiply
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// pipeline is a two stage pipeline, so we need
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// two bits in the pipe.
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mpypipe[0] <= (i_ce)&&((i_op[3:1]==3'h5)
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||(i_op[3:0]==4'h8));
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mpypipe[1] <= mpypipe[0];
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if (i_op[0]) // i.e. if signed multiply
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begin
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r_mpy_a_input <= {(~i_a[31]),i_a[30:0]};
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r_mpy_b_input <= {(~i_b[31]),i_b[30:0]};
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end else begin
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r_mpy_a_input <= i_a[31:0];
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r_mpy_b_input <= i_b[31:0];
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end
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// The signed bit really only matters in the
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// case of 64 bit multiply. We'll keep track
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// of it, though, and pretend in all other
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// cases.
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r_mpy_signed <= i_op[0];
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if (i_ce)
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mpyhi = i_op[1];
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end
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assign mpybusy = |mpypipe;
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// Second clock, do the multiplies, get the "partial
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// products". Here, we break our input up into two
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// halves,
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//
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// A = (2^16 ah + al)
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// B = (2^16 bh + bl)
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//
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// and use these to compute partial products.
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//
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// AB = (2^32 ah*bh + 2^16 (ah*bl + al*bh) + (al*bl)
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//
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// Since we're following the FOIL algorithm to get here,
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// we'll name these partial products according to FOIL.
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//
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// The trick is what happens if A or B is signed. In
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// those cases, the real value of A will not be given by
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// A = (2^16 ah + al)
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// but rather
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// A = (2^16 ah[31^] + al) - 2^31
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// (where we have flipped the sign bit of A)
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// and so ...
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//
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// AB= (2^16 ah + al - 2^31) * (2^16 bh + bl - 2^31)
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// = 2^32(ah*bh)
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// +2^16 (ah*bl+al*bh)
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// +(al*bl)
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// - 2^31 (2^16 bh+bl + 2^16 ah+al)
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// - 2^62
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// = 2^32(ah*bh)
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// +2^16 (ah*bl+al*bh)
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// +(al*bl)
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// - 2^31 (2^16 bh+bl + 2^16 ah+al + 2^31)
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//
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reg [31:0] pp_f, pp_l; // pp_o, pp_i, pp_l;
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reg [32:0] pp_oi;
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reg [32:0] pp_s;
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always @(posedge i_clk)
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begin
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pp_f<=r_mpy_a_input[31:16]*r_mpy_b_input[31:16];
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pp_oi<=r_mpy_a_input[31:16]*r_mpy_b_input[15: 0]
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+ r_mpy_a_input[15: 0]*r_mpy_b_input[31:16];
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pp_l<=r_mpy_a_input[15: 0]*r_mpy_b_input[15: 0];
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// And a special one for the sign
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if (r_mpy_signed)
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pp_s <= 32'h8000_0000-(
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r_mpy_a_input[31:0]
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+ r_mpy_b_input[31:0]);
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else
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pp_s <= 33'h0;
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end
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// Third clock, add the results and produce a product
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always @(posedge i_clk)
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begin
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r_mpy_result[15:0] <= pp_l[15:0];
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r_mpy_result[63:16] <=
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{ 32'h00, pp_l[31:16] }
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+ { 15'h00, pp_oi }
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+ { pp_s, 15'h00 }
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+ { pp_f, 16'h00 };
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end
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end // Fourth clock -- results are available for writeback.
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`else
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wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
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wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
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wire [33:0] w_mpy_result;
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wire [33:0] w_mpy_result;
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reg [31:0] r_mpy_result;
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reg [31:0] r_mpy_result;
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assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
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assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
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assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
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assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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r_mpy_result = w_mpy_result[31:0];
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r_mpy_result = w_mpy_result[31:0];
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`endif
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//
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//
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// The master ALU case statement
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// The master ALU case statement
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//
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//
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always @(posedge i_clk)
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always @(posedge i_clk)
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| Line 159... |
Line 296... |
4'b0011: o_c <= i_a | i_b; // Or
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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`ifdef LONG_MPY
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4'b1000: o_c <= r_mpy_result[31:0]; // MPY
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`else
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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`endif
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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`ifdef LONG_MPY
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4'b1010: o_c <= r_mpy_result[63:32]; // MPYHU
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4'b1011: o_c <= r_mpy_result[63:32]; // MPYHS
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`else
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4'b1010: o_c <= r_mpy_result; // MPYU
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4'b1010: o_c <= r_mpy_result; // MPYU
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4'b1011: o_c <= r_mpy_result; // MPYS
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4'b1011: o_c <= r_mpy_result; // MPYS
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`endif
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1110: o_c <= w_rol_result; // ROL
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4'b1110: o_c <= w_rol_result; // ROL
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default: o_c <= i_b; // MOV, LDI
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default: o_c <= i_b; // MOV, LDI
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endcase
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endcase
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end else if (r_busy)
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end else if (r_busy)
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`ifdef LONG_MPY
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o_c <= (mpyhi)?r_mpy_result[63:32]:r_mpy_result[31:0];
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`else
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o_c <= r_mpy_result;
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o_c <= r_mpy_result;
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`endif
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reg r_busy;
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reg r_busy;
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initial r_busy = 1'b0;
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initial r_busy = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
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r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
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`ifdef LONG_MPY
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&&((i_op[3:1] == 3'h5)
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||(i_op[3:0] == 4'h8))||mpybusy;
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`else
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&&(i_op[3:1] == 3'h5);
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&&(i_op[3:1] == 3'h5);
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`endif
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assign o_busy = r_busy;
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assign o_busy = r_busy;
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assign o_illegal = 1'b0;
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assign o_illegal = 1'b0;
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end endgenerate
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end endgenerate
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| Line 193... |
Line 348... |
initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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else
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else
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o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)
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o_valid <= (i_ce)&&(i_valid)
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||(o_busy);
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`ifdef LONG_MPY
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&&(i_op[3:1] != 3'h5)&&(i_op[3:0] != 4'h8)
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||(o_busy)&&(~mpybusy);
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`else
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&&(i_op[3:1] != 3'h5)||(o_busy);
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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