| Line 69... |
Line 69... |
output reg o_illegal;
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output reg o_illegal;
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output reg [(AW-1):0] o_pc;
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output reg [(AW-1):0] o_pc;
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output reg o_gie;
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output reg o_gie;
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output reg [6:0] o_dcdR, o_dcdA, o_dcdB;
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output reg [6:0] o_dcdR, o_dcdA, o_dcdB;
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output wire [31:0] o_I;
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output wire [31:0] o_I;
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output reg o_zI;
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output wire o_zI;
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output reg [3:0] o_cond;
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output reg [3:0] o_cond;
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output reg o_wF;
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output reg o_wF;
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output reg [3:0] o_op;
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output reg [3:0] o_op;
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output reg o_ALU, o_M, o_DV, o_FP, o_break;
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output reg o_ALU, o_M, o_DV, o_FP, o_break;
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output wire o_lock;
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output wire o_lock;
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| Line 84... |
Line 84... |
output wire o_pipe;
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output wire o_pipe;
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|
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wire dcdA_stall, dcdB_stall, dcdF_stall;
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wire dcdA_stall, dcdB_stall, dcdF_stall;
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wire o_dcd_early_branch;
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wire o_dcd_early_branch;
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wire [(AW-1):0] o_dcd_branch_pc;
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wire [(AW-1):0] o_dcd_branch_pc;
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reg o_dcdI, o_dcdIz;
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`ifdef OPT_PIPELINED
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`ifdef OPT_PIPELINED
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reg r_lock, r_pipe;
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reg r_lock, r_pipe, r_zI;
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`endif
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`endif
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wire [4:0] w_op;
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wire [4:0] w_op;
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wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
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wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
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| Line 341... |
Line 340... |
o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
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o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
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o_wR <= w_wR;
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o_wR <= w_wR;
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o_rA <= w_rA;
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o_rA <= w_rA;
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o_rB <= w_rB;
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o_rB <= w_rB;
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r_I <= w_I;
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r_I <= w_I;
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o_zI <= w_Iz;
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`ifdef OPT_PIPELINED
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r_zI <= w_Iz;
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`endif
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|
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// Turn a NOOP into an ALU operation--subtract in
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// Turn a NOOP into an ALU operation--subtract in
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// particular, although it doesn't really matter as long
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// particular, although it doesn't really matter as long
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// as it doesn't take longer than one clock. Note
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// as it doesn't take longer than one clock. Note
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// also that this depends upon not setting any registers
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// also that this depends upon not setting any registers
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| Line 366... |
Line 367... |
`endif
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`endif
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end
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end
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|
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`ifdef OPT_PIPELINED
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`ifdef OPT_PIPELINED
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assign o_lock = r_lock;
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assign o_lock = r_lock;
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assign o_zI = r_zI;
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`else
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`else
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assign o_lock = 1'b0;
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assign o_lock = 1'b0;
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assign o_zI = 1'b0;
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`endif
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`endif
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|
|
generate
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generate
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if (EARLY_BRANCHING!=0)
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if (EARLY_BRANCHING!=0)
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begin
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begin
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| Line 440... |
Line 443... |
// 4. Both must be to the same address, or the address incremented
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// 4. Both must be to the same address, or the address incremented
|
// by one
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// by one
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// Note that we're not using iword here ... there's a lot of logic
|
// Note that we're not using iword here ... there's a lot of logic
|
// taking place, and it's only valid if the new word is not compressed.
|
// taking place, and it's only valid if the new word is not compressed.
|
//
|
//
|
reg r_valid;
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
|
reg r_valid;
|
reg r_pipe;
|
reg r_pipe;
|
initial r_pipe = 1'b0;
|
initial r_pipe = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_ce)
|
if (i_ce)
|
r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
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r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
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| Line 456... |
Line 459... |
&&((i_instruction[21:19]==o_cond[2:0])
|
&&((i_instruction[21:19]==o_cond[2:0])
|
||(o_cond[2:0] == 3'h0))
|
||(o_cond[2:0] == 3'h0))
|
&&((i_instruction[13:0]==r_I[13:0])
|
&&((i_instruction[13:0]==r_I[13:0])
|
||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
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||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
|
assign o_pipe = r_pipe;
|
assign o_pipe = r_pipe;
|
`else
|
|
assign o_pipe = 1'b0;
|
|
`endif
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_valid <= 1'b0;
|
r_valid <= 1'b0;
|
else if ((i_ce)&&(o_ljmp))
|
else if ((i_ce)&&(o_ljmp))
|
r_valid <= 1'b0;
|
r_valid <= 1'b0;
|
else if ((i_ce)&&(i_pf_valid))
|
else if ((i_ce)&&(i_pf_valid))
|
r_valid <= 1'b1;
|
r_valid <= 1'b1;
|
else if (~i_stalled)
|
else if (~i_stalled)
|
r_valid <= 1'b0;
|
r_valid <= 1'b0;
|
|
`else
|
|
assign o_pipe = 1'b0;
|
|
`endif
|
|
|
|
|
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
|
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
|
|
|
endmodule
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endmodule
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