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[/] [s6soc/] [trunk/] [rtl/] [cpu/] [idecode.v] - Diff between revs 11 and 30

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Rev 11 Rev 30
Line 69... Line 69...
        output  reg             o_illegal;
        output  reg             o_illegal;
        output  reg     [(AW-1):0]       o_pc;
        output  reg     [(AW-1):0]       o_pc;
        output  reg             o_gie;
        output  reg             o_gie;
        output  reg     [6:0]    o_dcdR, o_dcdA, o_dcdB;
        output  reg     [6:0]    o_dcdR, o_dcdA, o_dcdB;
        output  wire    [31:0]   o_I;
        output  wire    [31:0]   o_I;
        output  reg             o_zI;
        output  wire            o_zI;
        output  reg     [3:0]    o_cond;
        output  reg     [3:0]    o_cond;
        output  reg             o_wF;
        output  reg             o_wF;
        output  reg     [3:0]    o_op;
        output  reg     [3:0]    o_op;
        output  reg             o_ALU, o_M, o_DV, o_FP, o_break;
        output  reg             o_ALU, o_M, o_DV, o_FP, o_break;
        output  wire            o_lock;
        output  wire            o_lock;
Line 84... Line 84...
        output  wire            o_pipe;
        output  wire            o_pipe;
 
 
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
        wire                    o_dcd_early_branch;
        wire                    o_dcd_early_branch;
        wire    [(AW-1):0]       o_dcd_branch_pc;
        wire    [(AW-1):0]       o_dcd_branch_pc;
        reg     o_dcdI, o_dcdIz;
 
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        reg     r_lock, r_pipe;
        reg     r_lock, r_pipe, r_zI;
`endif
`endif
 
 
 
 
        wire    [4:0]    w_op;
        wire    [4:0]    w_op;
        wire            w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
        wire            w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
Line 341... Line 340...
                        o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
                        o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
                        o_wR  <= w_wR;
                        o_wR  <= w_wR;
                        o_rA  <= w_rA;
                        o_rA  <= w_rA;
                        o_rB  <= w_rB;
                        o_rB  <= w_rB;
                        r_I    <= w_I;
                        r_I    <= w_I;
                        o_zI   <= w_Iz;
`ifdef  OPT_PIPELINED
 
                        r_zI   <= w_Iz;
 
`endif
 
 
                        // Turn a NOOP into an ALU operation--subtract in 
                        // Turn a NOOP into an ALU operation--subtract in 
                        // particular, although it doesn't really matter as long
                        // particular, although it doesn't really matter as long
                        // as it doesn't take longer than one clock.  Note
                        // as it doesn't take longer than one clock.  Note
                        // also that this depends upon not setting any registers
                        // also that this depends upon not setting any registers
Line 366... Line 367...
`endif
`endif
                end
                end
 
 
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        assign  o_lock = r_lock;
        assign  o_lock = r_lock;
 
        assign  o_zI = r_zI;
`else
`else
        assign  o_lock = 1'b0;
        assign  o_lock = 1'b0;
 
        assign  o_zI = 1'b0;
`endif
`endif
 
 
        generate
        generate
        if (EARLY_BRANCHING!=0)
        if (EARLY_BRANCHING!=0)
        begin
        begin
Line 440... Line 443...
        //      4. Both must be to the same address, or the address incremented
        //      4. Both must be to the same address, or the address incremented
        //              by one
        //              by one
        // Note that we're not using iword here ... there's a lot of logic
        // Note that we're not using iword here ... there's a lot of logic
        // taking place, and it's only valid if the new word is not compressed.
        // taking place, and it's only valid if the new word is not compressed.
        //
        //
        reg     r_valid;
 
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
 
        reg     r_valid;
        reg     r_pipe;
        reg     r_pipe;
        initial r_pipe = 1'b0;
        initial r_pipe = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_ce)
                if (i_ce)
                        r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
                        r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
Line 456... Line 459...
                                &&((i_instruction[21:19]==o_cond[2:0])
                                &&((i_instruction[21:19]==o_cond[2:0])
                                        ||(o_cond[2:0] == 3'h0))
                                        ||(o_cond[2:0] == 3'h0))
                                &&((i_instruction[13:0]==r_I[13:0])
                                &&((i_instruction[13:0]==r_I[13:0])
                                        ||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
                                        ||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
        assign o_pipe = r_pipe;
        assign o_pipe = r_pipe;
`else
 
        assign o_pipe = 1'b0;
 
`endif
 
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_valid <= 1'b0;
                        r_valid <= 1'b0;
                else if ((i_ce)&&(o_ljmp))
                else if ((i_ce)&&(o_ljmp))
                        r_valid <= 1'b0;
                        r_valid <= 1'b0;
                else if ((i_ce)&&(i_pf_valid))
                else if ((i_ce)&&(i_pf_valid))
                        r_valid <= 1'b1;
                        r_valid <= 1'b1;
                else if (~i_stalled)
                else if (~i_stalled)
                        r_valid <= 1'b0;
                        r_valid <= 1'b0;
 
`else
 
        assign o_pipe = 1'b0;
 
`endif
 
 
 
 
        assign  o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
        assign  o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
 
 
endmodule
endmodule

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