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[/] [s6soc/] [trunk/] [rtl/] [cpu/] [zipcpu.v] - Diff between revs 23 and 30

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Rev 23 Rev 30
Line 469... Line 469...
                        &&(~clear_pipeline);
                        &&(~clear_pipeline);
`else
`else
        // If we aren't pipelined, then no one will be changing what's in the
        // If we aren't pipelined, then no one will be changing what's in the
        // pipeline (i.e. clear_pipeline), while our only instruction goes
        // pipeline (i.e. clear_pipeline), while our only instruction goes
        // through the ... pipeline.
        // through the ... pipeline.
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline);
        //
 
        // However, in hind sight this logic didn't work.  What happens when
 
        // something gets in the pipeline and then (due to interrupt or some
 
        // such) needs to be voided?  Thus we avoid simplification and keep
 
        // what worked here.
 
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
 
                        &&(~clear_pipeline);
`endif
`endif
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
                                (mem_pipe_stalled)
                                (mem_pipe_stalled)
                                ||((~op_pipe)&&(mem_busy))
                                ||((~op_pipe)&&(mem_busy))
Line 619... Line 625...
        // However ... we need to know this before this clock, hence this is
        // However ... we need to know this before this clock, hence this is
        // calculated in the instruction decoder.
        // calculated in the instruction decoder.
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        r_op_pipe <= dcd_pipe;
                        r_op_pipe <= dcd_pipe;
 
                else if (mem_ce) // Clear us any time an op_ is clocked in
 
                        r_op_pipe <= 1'b0;
        assign  op_pipe = r_op_pipe;
        assign  op_pipe = r_op_pipe;
`else
`else
        assign  op_pipe = 1'b0;
        assign  op_pipe = 1'b0;
`endif
`endif
 
 
Line 991... Line 999...
                                // We'll use the last values from that stage
                                // We'll use the last values from that stage
                                // (opR_wr, opF_wr, opR) in our logic below.
                                // (opR_wr, opF_wr, opR) in our logic below.
                                &&((opvalid)||(mem_rdbusy)
                                &&((opvalid)||(mem_rdbusy)
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
                                &&(
                                &&(
                                // Stall on memory ops writing to my register
                                // Okay, what happens if the result register
                                //      (i.e. loads), or on any write to my
                                // from instruction 1 becomes the input for
                                //      register if I have an immediate offset
                                // instruction two, *and* there's an immediate
                                //      Actually, this is worse.  I can't tell
                                // offset in instruction two?  In that case, we
                                //      whether or not my register is going to
                                // need an extra clock between the two 
                                //      be written to, so 
                                // instructions to calculate the base plus 
                                // Note the exception for writing to the PC:
                                // offset.
                                //      if I write to the PC, the whole next
                                //
                                //      instruction is invalid, not just the
                                // What if instruction 1 (or before) is in a
                                //      operand.  That'll get wiped in the
                                // memory pipeline?  We may no longer know what
                                //      next operation anyway, so don't stall
                                // the register was!  We will then need  to 
                                //      here.  This keeps a BC X, BNZ Y from
                                // blindly wait.  We'll temper this only waiting
                                //      stalling between the two branches.
                                // if we're not piping this new instruction.
                                //      BC X, BRA Y is still clear, since BRA Y
                                // If we were piping, the pipe logic in the
                                //      is an early branch instruction.
                                // decode circuit has told us that the hazard
                                //      (This exception is commented out in
                                // is clear, so we're okay then.
                                //      order to help keep our logic simple, and
 
                                //      because multiple conditional branches
 
                                //      following each other constitutes a
 
                                //      fairly unusualy code structure.)
 
                                //      
                                //      
                                ((~dcd_zI)&&(
                                ((~dcd_zI)&&(
                                        ((opR == dcdB)&&(opR_wr))
                                        ((opR == dcdB)&&(opR_wr))
                                        ||(((opvalid_mem)||(mem_rdbusy))
                                        ||((mem_rdbusy)&&(~dcd_pipe))
                                        &&(op_pipe))))
                                        ))
                                // Stall following any instruction that will
                                // Stall following any instruction that will
                                // set the flags, if we're going to need the
                                // set the flags, if we're going to need the
                                // flags (CC) register for opB.
                                // flags (CC) register for opB.
                                ||((opF_wr)&&(dcdB_cc))
                                ||((opF_wr)&&(dcdB_cc))
                                // Stall on any ongoing memory operation that
                                // Stall on any ongoing memory operation that

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