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//      The difference between these control signals allows individual stages

//      The difference between these control signals allows individual stages

//      to propagate instructions independently.  In general, the logic works

//      to propagate instructions independently.  In general, the logic works

//      as:

//      as:

//

//

//

//

//

//

//

//

//      always @(posedge i_clk)

//      always @(posedge i_clk)

//              if ((i_rst)||(clear_pipeline))

//              if ((i_rst)||(clear_pipeline))

//                      (n)_valid = 0

//                      (n)_valid = 0

        wire    [3:0]    dcd_F;

        wire    [3:0]    dcd_F;

        wire            dcd_wR, dcd_rA, dcd_rB,

        wire            dcd_wR, dcd_rA, dcd_rB,

                                dcd_ALU, dcd_M, dcd_DIV, dcd_FP,

                                dcd_ALU, dcd_M, dcd_DIV, dcd_FP,

                                dcd_wF, dcd_gie, dcd_break, dcd_lock,

                                dcd_wF, dcd_gie, dcd_break, dcd_lock,

                                dcd_pipe, dcd_ljmp;

                                dcd_pipe, dcd_ljmp;

        wire            dcd_valid;

        wire            dcd_valid;

        wire    [AW:0]   dcd_pc /* verilator public_flat */;

        wire    [AW:0]   dcd_pc /* verilator public_flat */;

        wire    [31:0]   dcd_I;

        wire    [31:0]   dcd_I;

        wire            dcd_zI; // true if dcd_I == 0

        wire            dcd_zI; // true if dcd_I == 0

        wire    dcd_A_stall, dcd_B_stall, dcd_F_stall;

        wire    dcd_A_stall, dcd_B_stall, dcd_F_stall;

        wire    [14:0]   op_Fl;

        wire    [14:0]   op_Fl;

        reg     [6:0]    r_op_F;

        reg     [6:0]    r_op_F;

        wire    [7:0]    op_F;

        wire    [7:0]    op_F;

        wire            op_ce, op_phase, op_pipe, op_change_data_ce;

        wire            op_ce, op_phase, op_pipe, op_change_data_ce;

        // Some pipeline control wires

        // Some pipeline control wires

        reg     op_illegal;

        reg     op_illegal;

        wire    op_break;

        wire    op_break;

        wire    op_lock;

        wire    op_lock;

`ifdef  VERILATOR

`ifdef  VERILATOR

        wire    div_ce, div_error, div_busy, div_valid;

        wire    div_ce, div_error, div_busy, div_valid;

        wire    [31:0]   div_result;

        wire    [31:0]   div_result;

        wire    [3:0]    div_flags;

        wire    [3:0]    div_flags;

                                &&(set_cond);

                                &&(set_cond);

        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;

        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;

        wire    [31:0]   fpu_result;

        wire    [31:0]   fpu_result;

        wire    [3:0]    fpu_flags;

        wire    [3:0]    fpu_flags;

                                &&(set_cond);

                                &&(set_cond);

        wire    adf_ce_unconditional;

        wire    adf_ce_unconditional;

        //

        //

        //

        //

        //      MASTER: clock enable.

        //      MASTER: clock enable.

        //

        //

        //

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //      PIPELINE STAGE #1 :: Prefetch

        //              Calculate stall conditions

        //              Calculate stall conditions

        //

        //

        //

        //

        //      PIPELINE STAGE #2 :: Instruction Decode

        //      PIPELINE STAGE #2 :: Instruction Decode

        //              Calculate stall conditions

        //              Calculate stall conditions

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

        assign          dcd_stalled = (dcd_valid)&&(op_stall);

        assign          dcd_stalled = (dcd_valid)&&(op_stall);

`endif

`endif

        //

        //

        //      PIPELINE STAGE #3 :: Read Operands

        //      PIPELINE STAGE #3 :: Read Operands

        //              Calculate stall conditions

        //              Calculate stall conditions

        wire    prelock_stall;

        wire    prelock_stall;

                        ||(mem_busy)||(div_busy)||(fpu_busy);

                        ||(mem_busy)||(div_busy)||(fpu_busy);

        assign  op_stall = (op_valid)&&( // Only stall if we're loaded w/validins

        assign  op_stall = (op_valid)&&( // Only stall if we're loaded w/validins

                        // Stall if we're stopped, and not allowed to execute

                        // Stall if we're stopped, and not allowed to execute

                        // an instruction

                        // an instruction

                        //

                        //

                        // Stall if going into the ALU and the ALU is stalled

                        // Stall if going into the ALU and the ALU is stalled

                        //      i.e. if the memory is busy, or we are single

                        //      i.e. if the memory is busy, or we are single

                        //      stepping.  This also includes our stalls for

                        //      stepping.  This also includes our stalls for

                        //      op_break and op_lock, so we don't need to

                        //      op_break and op_lock, so we don't need to

                                // CC register

                                // CC register

                                ||(dcd_F_stall)

                                ||(dcd_F_stall)

                        );

                        );

        assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);

        assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);

        // BUT ... op_ce is too complex for many of the data operations.  So

        // BUT ... op_ce is too complex for many of the data operations.  So

        // let's make their circuit enable code simpler.  In particular, if

        // let's make their circuit enable code simpler.  In particular, if

        // op_ doesn't need to be preserved, we can change it all we want

        // op_ doesn't need to be preserved, we can change it all we want

        // ... right?  The clear_pipeline code, for example, really only needs

        // ... right?  The clear_pipeline code, for example, really only needs

        // to determine whether op_valid is true.

        // to determine whether op_valid is true.

        //

        //

        //      PIPELINE STAGE #4 :: ALU / Memory

        //      PIPELINE STAGE #4 :: ALU / Memory

        //              Calculate stall conditions

        //              Calculate stall conditions

        //

        //

        //      since we don't know if it'll put us to sleep or not.

        //      since we don't know if it'll put us to sleep or not.

        // 4. Last case: Stall if we would otherwise move a break instruction

        // 4. Last case: Stall if we would otherwise move a break instruction

        //      through the ALU.  Break instructions are not allowed through

        //      through the ALU.  Break instructions are not allowed through

        //      the ALU.

        //      the ALU.

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

                        ||(prelock_stall)

                        ||(prelock_stall)

                        ||((op_valid)&&(op_break))

                        ||((op_valid)&&(op_break))

                        ||(wr_reg_ce)&&(wr_write_cc)

                        ||(wr_reg_ce)&&(wr_write_cc)

                        ||(div_busy)||(fpu_busy);

                        ||(div_busy)||(fpu_busy);

`else

`else

`endif

`endif

        //

        //

        //

        //

        // Note: if you change the conditions for mem_ce, you must also change

        // Note: if you change the conditions for mem_ce, you must also change

        // alu_pc_valid.

        // alu_pc_valid.

        //

        //

`ifdef  OPT_PIPELINED_BUS_ACCESS

`ifdef  OPT_PIPELINED_BUS_ACCESS

                                (mem_pipe_stalled)

                                (mem_pipe_stalled)

                                ||(prelock_stall)

                                ||(prelock_stall)

                                ||(div_busy)

                                ||(div_busy)

                                ||(fpu_busy)

                                ||(fpu_busy)

                                // Stall waiting for flags to be valid

                                // Stall waiting for flags to be valid

                                // Or waiting for a write to the PC register

                                // Or waiting for a write to the PC register

                                // Or CC register, since that can change the

                                // Or CC register, since that can change the

                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)

                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)

                                        &&((wr_write_pc)||(wr_write_cc)))));

                                        &&((wr_write_pc)||(wr_write_cc)))));

`else

`else

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

        assign  mem_stalled = (mem_busy)||((op_valid_mem)&&(

        assign  mem_stalled = (mem_busy)||((op_valid_mem)&&(

                                // Stall waiting for flags to be valid

                                // Stall waiting for flags to be valid

                                // Or waiting for a write to the PC register

                                // Or waiting for a write to the PC register

                                // Or CC register, since that can change the

                                // Or CC register, since that can change the

                                //  PC as well

                                //  PC as well

                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));

                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));

`else

`else

`endif

`endif

`endif

`endif

        // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these

        // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these

        //

        //

        //

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //      PIPELINE STAGE #1 :: Prefetch

        //

        //

        //

        //

        prefetch        #(ADDRESS_WIDTH)

        prefetch        #(ADDRESS_WIDTH)

                                        pf_valid, pf_illegal,

                                        pf_valid, pf_illegal,

                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,

                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,

                                pf_ack, pf_stall, pf_err, i_wb_data);

                                pf_ack, pf_stall, pf_err, i_wb_data);

`ifdef  OPT_TRADITIONAL_PFCACHE

`ifdef  OPT_TRADITIONAL_PFCACHE

        pfcache #(LGICACHE, ADDRESS_WIDTH)

        pfcache #(LGICACHE, ADDRESS_WIDTH)

                                // dcd_pc,

                                // dcd_pc,

                                (!pf_stalled),

                                (!pf_stalled),

                                pf_request_address,

                                pf_request_address,

                                pf_instruction, pf_instruction_pc, pf_valid,

                                pf_instruction, pf_instruction_pc, pf_valid,

                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,

                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,

                                        pf_ack, pf_stall, pf_err, i_wb_data,

                                        pf_ack, pf_stall, pf_err, i_wb_data,

                                pf_illegal);

                                pf_illegal);

`else

`else

        pipefetch       #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH)

        pipefetch       #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH)

                                        w_clear_icache, (!pf_stalled),

                                        w_clear_icache, (!pf_stalled),

                                        (new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc,

                                        (new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc,

                                        pf_instruction, pf_instruction_pc, pf_valid,

                                        pf_instruction, pf_instruction_pc, pf_valid,

                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,

                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,

                                        pf_ack, pf_stall, pf_err, i_wb_data,

                                        pf_ack, pf_stall, pf_err, i_wb_data,

                                (mem_cyc_lcl)||(mem_cyc_gbl),

                                (mem_cyc_lcl)||(mem_cyc_gbl),

                                pf_illegal);

                                pf_illegal);

        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,

        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,

                        IMPLEMENT_FPU)

                        IMPLEMENT_FPU)

                        dcd_illegal, dcd_pc, dcd_gie,

                        dcd_illegal, dcd_pc, dcd_gie,

                        { dcd_Rcc, dcd_Rpc, dcd_R },

                        { dcd_Rcc, dcd_Rpc, dcd_R },

                        { dcd_Acc, dcd_Apc, dcd_A },

                        { dcd_Acc, dcd_Apc, dcd_A },

                        { dcd_Bcc, dcd_Bpc, dcd_B },

                        { dcd_Bcc, dcd_Bpc, dcd_B },

                        dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn,

                        dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn,

                        op_rB <= dcd_rB;

                        op_rB <= dcd_rB;

                end

                end

`endif

`endif

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (op_ce)

                if (op_ce)

                begin

                begin

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

                        if ((wr_reg_ce)&&(wr_reg_id == dcd_A))

                        if ((wr_reg_ce)&&(wr_reg_id == dcd_A))

                                r_op_Av <= wr_gpreg_vl;

                                r_op_Av <= wr_gpreg_vl;

                        else

                        else

                                r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags };

                                r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags };

                        else

                        else

                                r_op_Av <= w_op_Av;

                                r_op_Av <= w_op_Av;

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

                end else

                end else

                        if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA))

                        if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA))

                                r_op_Av <= wr_gpreg_vl;

                                r_op_Av <= wr_gpreg_vl;

`endif

`endif

                end

                end

        // conditions checking those bits.  Therefore, Vivado complains that

        // conditions checking those bits.  Therefore, Vivado complains that

        // these two bits are redundant.  Hence the convoluted expression

        // these two bits are redundant.  Hence the convoluted expression

        // below, arriving at what we finally want in the (now wire net)

        // below, arriving at what we finally want in the (now wire net)

        // op_F.

        // op_F.

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (op_ce) // Cannot do op_change_data_ce here since op_F depends

                if (op_ce) // Cannot do op_change_data_ce here since op_F depends

                        // upon being either correct for a valid op, or correct

                        // upon being either correct for a valid op, or correct

                        // for the last valid op

                        // for the last valid op

                begin // Set the flag condition codes, bit order is [3:0]=VNCZ

                begin // Set the flag condition codes, bit order is [3:0]=VNCZ

                        case(dcd_F[2:0])

                        case(dcd_F[2:0])

                        3'h0:   r_op_F <= 7'h00;        // Always

                        3'h0:   r_op_F <= 7'h00;        // Always

                        3'h1:   r_op_F <= 7'h11;        // Z

                        3'h1:   r_op_F <= 7'h11;        // Z

                        3'h2:   r_op_F <= 7'h44;        // LT

                        3'h2:   r_op_F <= 7'h44;        // LT

                        endcase

                        endcase

                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }

                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }

        assign  op_F = { r_op_F[3], r_op_F[6:0] };

        assign  op_F = { r_op_F[3], r_op_F[6:0] };

        wire    w_op_valid;

        wire    w_op_valid;

        initial op_valid     = 1'b0;

        initial op_valid     = 1'b0;

        initial op_valid_alu = 1'b0;

        initial op_valid_alu = 1'b0;

        initial op_valid_mem = 1'b0;

        initial op_valid_mem = 1'b0;

        initial op_valid_div = 1'b0;

        initial op_valid_div = 1'b0;

        initial op_valid_fpu = 1'b0;

        initial op_valid_fpu = 1'b0;

                        //   wait until our operands are valid, then we aren't

                        //   wait until our operands are valid, then we aren't

                        //   valid yet until then.

                        //   valid yet until then.

                        op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch);

                        op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch);

                        op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal)

                        op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal)

                                        ||(dcd_early_branch));

                                        ||(dcd_early_branch));

                end else if ((adf_ce_unconditional)||(mem_ce))

                end else if ((adf_ce_unconditional)||(mem_ce))

                begin

                begin

                        op_valid     <= 1'b0;

                        op_valid     <= 1'b0;

                        op_valid_alu <= 1'b0;

                        op_valid_alu <= 1'b0;

                        op_valid_mem <= 1'b0;

                        op_valid_mem <= 1'b0;

        // break to repeat and continue upon return.  To get out of this

        // break to repeat and continue upon return.  To get out of this

        // condition, replace the break instruction with what it is supposed

        // condition, replace the break instruction with what it is supposed

        // to be, step through it, and then replace it back.  In this fashion,

        // to be, step through it, and then replace it back.  In this fashion,

        // a debugger can step through code.

        // a debugger can step through code.

        // assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001);

        // assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001);

        reg     r_op_break;

        reg     r_op_break;

        initial r_op_break = 1'b0;

        initial r_op_break = 1'b0;

        always @(posedge i_clk)

        always @(posedge i_clk)

                if ((i_rst)||(clear_pipeline))  r_op_break <= 1'b0;

                if ((i_rst)||(clear_pipeline))  r_op_break <= 1'b0;

                else if (op_ce)

                else if (op_ce)

                        r_op_break <= (dcd_break);

                        r_op_break <= (dcd_break);

                else if (!op_valid)

                else if (!op_valid)

                        r_op_break <= 1'b0;

                        r_op_break <= 1'b0;

        assign  op_break = r_op_break;

        assign  op_break = r_op_break;

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

        generate

        generate

        if (IMPLEMENT_LOCK != 0)

        if (IMPLEMENT_LOCK != 0)

        begin

        begin

                initial r_op_lock = 1'b0;

                initial r_op_lock = 1'b0;

                always @(posedge i_clk)

                always @(posedge i_clk)

                        if (clear_pipeline)

                        if (clear_pipeline)

                                r_op_lock <= 1'b0;

                                r_op_lock <= 1'b0;

                        else if (op_ce)

                        else if (op_ce)

                assign  op_lock = r_op_lock;

                assign  op_lock = r_op_lock;

        end else begin

        end else begin

                assign  op_lock = 1'b0;

                assign  op_lock = 1'b0;

        end endgenerate

        end endgenerate

        // this logic should just optimize.

        // this logic should just optimize.

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (op_ce)

                if (op_ce)

                begin

                begin

                end

                end

`else

`else

        always @(posedge i_clk)

        always @(posedge i_clk)

        begin

        begin

        end

        end

`endif

`endif

`ifdef  VERILATOR

`ifdef  VERILATOR

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (op_change_data_ce)

                if (op_change_data_ce)

                begin

                begin

                        op_sim      <= dcd_sim;

                        op_sim      <= dcd_sim;

                        op_sim_immv <= dcd_sim_immv;

                        op_sim_immv <= dcd_sim_immv;

                end

                end

`endif

`endif

`endif

`endif

        reg     [3:0]    r_op_opn;

        reg     [3:0]    r_op_opn;

        reg     [4:0]    r_op_R;

        reg     [4:0]    r_op_R;

        reg             r_op_Rcc;

        reg             r_op_Rcc;

        reg             r_op_gie;

        reg             r_op_gie;

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (op_change_data_ce)

                if (op_change_data_ce)

                begin

                begin

                        // Which ALU operation?  Early branches are

                        // Which ALU operation?  Early branches are

                        // unimplemented moves

                        // unimplemented moves

                        //

                        //

                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];

                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];

                end

                end

        assign  op_opn = r_op_opn;

        assign  op_opn = r_op_opn;

        assign  op_R = r_op_R;

        assign  op_R = r_op_R;

        assign  op_gie = r_op_gie;

        assign  op_gie = r_op_gie;

        assign  op_Rcc = r_op_Rcc;

        assign  op_Rcc = r_op_Rcc;

        assign  op_Fl = (op_gie)?(w_uflags):(w_iflags);

        assign  op_Fl = (op_gie)?(w_uflags):(w_iflags);

`ifdef  OPT_CIS

`ifdef  OPT_CIS

        reg     r_op_phase;

        reg     r_op_phase;

        initial r_op_phase = 1'b0;

        initial r_op_phase = 1'b0;

                                // if we're not piping this new instruction.

                                // if we're not piping this new instruction.

                                // If we were piping, the pipe logic in the

                                // If we were piping, the pipe logic in the

                                // decode circuit has told us that the hazard

                                // decode circuit has told us that the hazard

                                // is clear, so we're okay then.

                                // is clear, so we're okay then.

                                //

                                //

                                        ((op_R == dcd_B)&&(op_wR))

                                        ((op_R == dcd_B)&&(op_wR))