| Line 187... |
Line 187... |
initial o_cs_n = 1'b1;
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initial o_cs_n = 1'b1;
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initial o_dat = 4'hd;
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initial o_dat = 4'hd;
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initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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initial o_busy = 1'b0;
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initial o_busy = 1'b0;
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initial r_input = 31'h000;
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initial r_input = 31'h000;
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initial o_mod = `QSPI_MOD_SPI;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((state == `QSPI_IDLE)&&(o_sck))
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if ((state == `QSPI_IDLE)&&(o_sck))
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begin
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begin
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o_cs_n <= 1'b1;
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o_cs_n <= 1'b1;
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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o_busy <= 1'b0;
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o_busy <= 1'b0;
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o_mod <= `QSPI_MOD_SPI;
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o_mod <= `QSPI_MOD_SPI;
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if (i_wr)
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begin
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r_word <= i_word;
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r_word <= i_word;
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state <= `QSPI_START;
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r_spd <= i_spd;
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r_spd <= i_spd;
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r_dir <= i_dir;
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r_dir <= i_dir;
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if (i_wr)
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begin
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state <= `QSPI_START;
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
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o_cs_n <= 1'b0;
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o_cs_n <= 1'b0;
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// o_sck <= 1'b1;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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o_sck <= 1'b1;
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end
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end
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end else if (state == `QSPI_START)
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end else if (state == `QSPI_START)
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begin // We come in here with sck high, stay here 'til sck is low
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begin // We come in here with sck high, stay here 'til sck is low
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o_sck <= 1'b0;
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o_sck <= 1'b0;
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if (o_sck == 1'b0)
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if (o_sck == 1'b0)
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| Line 222... |
Line 223... |
o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
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o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
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o_cs_n <= 1'b0;
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o_cs_n <= 1'b0;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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if (r_spd)
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if (r_spd)
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begin
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o_dat <= r_word[31:28];
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o_dat <= r_word[31:28];
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// r_word <= { r_word[27:0], 4'h0 };
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else
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end else begin
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o_dat <= { 3'b110, r_word[31] };
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o_dat <= { 3'b110, r_word[31] };
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// r_word <= { r_word[30:0], 1'b0 };
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end
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end else if (~o_sck)
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end else if (~o_sck)
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begin
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begin
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o_sck <= 1'b1;
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o_sck <= 1'b1;
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o_busy <= ((state != `QSPI_READY)||(~i_wr));
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o_busy <= ((state != `QSPI_READY)||(~i_wr));
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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| Line 270... |
Line 267... |
// This is the state on the last clock (both low and
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// This is the state on the last clock (both low and
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// high clocks) of the data. Data is valid during
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// high clocks) of the data. Data is valid during
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// this state. Here we chose to either STOP or
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// this state. Here we chose to either STOP or
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// continue and transmit more.
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// continue and transmit more.
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o_sck <= (i_hold); // No clocks while holding
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o_sck <= (i_hold); // No clocks while holding
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r_spd <= i_spd;
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r_dir <= i_dir;
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if (i_spd)
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begin
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r_word <= { i_word[27:0], 4'h0 };
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h4;
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end else begin
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r_word <= { i_word[30:0], 1'b0 };
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h1;
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end
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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begin
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begin
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state <= `QSPI_BITS;
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state <= `QSPI_BITS;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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o_sck <= 1'b0;
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o_sck <= 1'b0;
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// Read the new request off the bus
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// Read the new request off the bus
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r_spd <= i_spd;
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r_dir <= i_dir;
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// Set up the first bits on the bus
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// Set up the first bits on the bus
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o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
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o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
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if (i_spd)
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if (i_spd)
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begin
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o_dat <= i_word[31:28];
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o_dat <= i_word[31:28];
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r_word <= { i_word[27:0], 4'h0 };
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else
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// spi_len <= spi_len - 4;
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
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- 6'h4;
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end else begin
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o_dat <= { 3'b110, i_word[31] };
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o_dat <= { 3'b110, i_word[31] };
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r_word <= { i_word[30:0], 1'b0 };
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
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- 6'h1;
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end
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// Read a bit upon any transition
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o_valid <= 1'b1;
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if (~o_mod[1])
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begin
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r_input <= { r_input[29:0], i_miso };
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o_word <= { r_input[30:0], i_miso };
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end else if (o_mod[1])
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begin
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r_input <= { r_input[26:0], i_dat };
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o_word <= { r_input[27:0], i_dat };
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end
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end else begin
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end else begin
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o_sck <= 1'b1;
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o_sck <= 1'b1;
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state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
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state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
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o_busy <= (~i_hold);
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o_busy <= (~i_hold);
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end
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// Read a bit upon any transition
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// Read a bit upon any transition
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o_valid <= 1'b1;
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o_valid <= 1'b1;
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if (~o_mod[1])
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if (~o_mod[1])
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begin
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begin
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| Line 322... |
Line 308... |
end else if (o_mod[1])
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end else if (o_mod[1])
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begin
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begin
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r_input <= { r_input[26:0], i_dat };
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r_input <= { r_input[26:0], i_dat };
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o_word <= { r_input[27:0], i_dat };
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o_word <= { r_input[27:0], i_dat };
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end
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end
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end
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end else if (state == `QSPI_HOLDING)
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end else if (state == `QSPI_HOLDING)
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begin
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begin
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// We need this state so that the o_valid signal
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// We need this state so that the o_valid signal
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// can get strobed with our last result. Otherwise
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// can get strobed with our last result. Otherwise
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// we could just sit in READY waiting for a new command.
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// we could just sit in READY waiting for a new command.
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| Line 336... |
Line 321... |
// commends in wbqspiflash for more details.
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// commends in wbqspiflash for more details.
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//
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//
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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o_cs_n <= 1'b0;
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o_cs_n <= 1'b0;
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o_busy <= 1'b0;
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o_busy <= 1'b0;
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r_spd <= i_spd;
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r_dir <= i_dir;
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if (i_spd)
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begin
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r_word <= { i_word[27:0], 4'h0 };
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spi_len<= { 1'b0, i_len, 3'b100 };
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end else begin
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r_word <= { i_word[30:0], 1'b0 };
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spi_len<= { 1'b0, i_len, 3'b111 };
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end
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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begin
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begin
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state <= `QSPI_BITS;
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state <= `QSPI_BITS;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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o_sck <= 1'b0;
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o_sck <= 1'b0;
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// Read the new request off the bus
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// Read the new request off the bus
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r_spd <= i_spd;
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r_dir <= i_dir;
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// Set up the first bits on the bus
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// Set up the first bits on the bus
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o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
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o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
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if (i_spd)
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if (i_spd)
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begin
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o_dat <= i_word[31:28];
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o_dat <= i_word[31:28];
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r_word <= { i_word[27:0], 4'h0 };
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else
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spi_len<= { 1'b0, i_len, 3'b100 };
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end else begin
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o_dat <= { 3'b110, i_word[31] };
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o_dat <= { 3'b110, i_word[31] };
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r_word <= { i_word[30:0], 1'b0 };
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spi_len<= { 1'b0, i_len, 3'b111 };
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end
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end else begin
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end else begin
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o_sck <= 1'b1;
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o_sck <= 1'b1;
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state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
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state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
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o_busy <= (~i_hold);
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o_busy <= (~i_hold);
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end
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end
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