/////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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// Filename: txuart.v
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// Filename: txuart.v
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//
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//
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// Project: FPGA library development (Spartan 3E development board)
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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//
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//
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// Purpose: Transmit outputs over a single UART line.
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// Purpose: Transmit outputs over a single UART line.
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//
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//
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// To interface with this module, connect it to your system clock,
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// To interface with this module, connect it to your system clock,
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// pass it the 32 bit setup register (defined below) and the byte
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// pass it the 32 bit setup register (defined below) and the byte
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// of data you wish to transmit. Strobe the i_wr line high for one
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// of data you wish to transmit. Strobe the i_wr line high for one
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// clock cycle, and your data will be off. Wait until the 'o_busy'
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// clock cycle, and your data will be off. Wait until the 'o_busy'
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// line is low before strobing the i_wr line again--this implementation
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// line is low before strobing the i_wr line again--this implementation
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// has NO BUFFER, so strobing i_wr while the core is busy will just
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// has NO BUFFER, so strobing i_wr while the core is busy will just
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// cause your data to be lost. The output will be placed on the o_txuart
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// cause your data to be lost. The output will be placed on the o_txuart
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// output line. If you wish to set/send a break condition, assert the
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// output line. If you wish to set/send a break condition, assert the
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// i_break line otherwise leave it low.
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// i_break line otherwise leave it low.
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//
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//
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// There is a synchronous reset line, logic high.
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// There is a synchronous reset line, logic high.
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//
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//
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// Now for the setup register. The register is 32 bits, so that this
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// Now for the setup register. The register is 32 bits, so that this
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// UART may be set up over a 32-bit bus.
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// UART may be set up over a 32-bit bus.
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//
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//
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// for a six bit word, or 2'b11 for a five bit word.
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// for a six bit word, or 2'b11 for a five bit word.
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//
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//
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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// Set this to one to expect two stop bits, zero for one.
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// Set this to one to expect two stop bits, zero for one.
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//
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//
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// i_setup[26] Indicates whether or not a parity bit exists. Set this
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// i_setup[26] Indicates whether or not a parity bit exists. Set this
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// to 1'b1 to include parity.
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// to 1'b1 to include parity.
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//
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//
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// i_setup[25] Indicates whether or not the parity bit is fixed. Set
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// i_setup[25] Indicates whether or not the parity bit is fixed. Set
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// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
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// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
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// parity to be set based upon data. (Both assume the parity
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// parity to be set based upon data. (Both assume the parity
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// enable value is set.)
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// enable value is set.)
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//
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//
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// i_setup[24] This bit is ignored if parity is not used. Otherwise,
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// i_setup[24] This bit is ignored if parity is not used. Otherwise,
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// in the case of a fixed parity bit, this bit indicates whether
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// in the case of a fixed parity bit, this bit indicates whether
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// mark (1'b1) or space (1'b0) parity is used. Likewise if the
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// mark (1'b1) or space (1'b0) parity is used. Likewise if the
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// parity is not fixed, a 1'b1 selects even parity, and 1'b0
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// parity is not fixed, a 1'b1 selects even parity, and 1'b0
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// selects odd.
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// selects odd.
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//
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//
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// i_setup[23:0] Indicates the speed of the UART in terms of clocks.
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// i_setup[23:0] Indicates the speed of the UART in terms of clocks.
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// So, for example, if you have a 200 MHz clock and wish to
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// So, for example, if you have a 200 MHz clock and wish to
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// run your UART at 9600 baud, you would take 200 MHz and divide
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// run your UART at 9600 baud, you would take 200 MHz and divide
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// by 9600 to set this value to 24'd20834. Likewise if you wished
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// by 9600 to set this value to 24'd20834. Likewise if you wished
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// to run this serial port at 115200 baud from a 200 MHz clock,
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// to run this serial port at 115200 baud from a 200 MHz clock,
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// you would set the value to 24'd1736
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// you would set the value to 24'd1736
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//
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//
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// Thus, to set the UART for the common setting of an 8-bit word,
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// Thus, to set the UART for the common setting of an 8-bit word,
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// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
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// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
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// would want to set the setup value to:
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// would want to set the setup value to:
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//
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//
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// 32'h0006c8 // For 115,200 baud, 8 bit, no parity
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// 32'h0006c8 // For 115,200 baud, 8 bit, no parity
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// 32'h005161 // For 9600 baud, 8 bit, no parity
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// 32'h005161 // For 9600 baud, 8 bit, no parity
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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// Copyright: 2015
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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/////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// This software is the ownership of Gisselquist Technology, LLC, and as
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// such it is proprietary. It is provided without any warrantees, either
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// express or implied, so that it may be tested. Upon completion, I ask
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// that working code be returned and not further distributed beyond those
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// that it is originally offered to.
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//
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//
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// Thank you.
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//
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//
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`define TXU_BIT_ZERO 4'h0
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`define TXU_BIT_ZERO 4'h0
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`define TXU_BIT_ONE 4'h1
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`define TXU_BIT_ONE 4'h1
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`define TXU_BIT_TWO 4'h2
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`define TXU_BIT_TWO 4'h2
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`define TXU_BIT_THREE 4'h3
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`define TXU_BIT_THREE 4'h3
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`define TXU_BIT_FOUR 4'h4
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`define TXU_BIT_FOUR 4'h4
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`define TXU_BIT_FIVE 4'h5
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`define TXU_BIT_FIVE 4'h5
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`define TXU_BIT_SIX 4'h6
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`define TXU_BIT_SIX 4'h6
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`define TXU_BIT_SEVEN 4'h7
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`define TXU_BIT_SEVEN 4'h7
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`define TXU_PARITY 4'h8 // Constant 1
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`define TXU_PARITY 4'h8 // Constant 1
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`define TXU_STOP 4'h9 // Constant 1
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`define TXU_STOP 4'h9 // Constant 1
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`define TXU_SECOND_STOP 4'ha
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`define TXU_SECOND_STOP 4'ha
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// 4'hb // Unused
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// 4'hb // Unused
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// 4'hc // Unused
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// 4'hc // Unused
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// `define TXU_START 4'hd // An unused state
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// `define TXU_START 4'hd // An unused state
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`define TXU_BREAK 4'he
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`define TXU_BREAK 4'he
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`define TXU_IDLE 4'hf
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`define TXU_IDLE 4'hf
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//
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module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy);
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//
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module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, i_cts, o_busy);
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input i_clk, i_reset;
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input i_clk, i_reset;
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input [29:0] i_setup;
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input [29:0] i_setup;
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input i_break;
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input i_break;
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input i_wr;
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input i_wr;
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input [7:0] i_data;
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input [7:0] i_data;
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output reg o_uart, o_busy;
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output reg o_uart;
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input i_cts;
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output wire o_busy;
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wire [27:0] clocks_per_baud, break_condition;
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wire [27:0] clocks_per_baud, break_condition;
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wire [1:0] data_bits;
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wire [1:0] data_bits;
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wire use_parity, parity_even, dblstop, fixd_parity;
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wire use_parity, parity_even, dblstop, fixd_parity;
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reg [29:0] r_setup;
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reg [29:0] r_setup;
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assign clocks_per_baud = { 4'h0, r_setup[23:0] };
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assign clocks_per_baud = { 4'h0, r_setup[23:0] };
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assign break_condition = { r_setup[23:0], 4'h0 };
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assign break_condition = { r_setup[23:0], 4'h0 };
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assign data_bits = r_setup[29:28];
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assign data_bits = r_setup[29:28];
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assign dblstop = r_setup[27];
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assign dblstop = r_setup[27];
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assign use_parity = r_setup[26];
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assign use_parity = r_setup[26];
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assign fixd_parity = r_setup[25];
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assign fixd_parity = r_setup[25];
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assign parity_even = r_setup[24];
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assign parity_even = r_setup[24];
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reg [27:0] baud_counter;
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reg [27:0] baud_counter;
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reg [3:0] state;
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reg [3:0] state;
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reg [7:0] lcl_data;
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reg [7:0] lcl_data;
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reg calc_parity;
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reg calc_parity;
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reg r_busy;
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initial o_uart = 1'b1;
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initial o_uart = 1'b1;
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initial o_busy = 1'b1;
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initial r_busy = 1'b1;
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initial state = `TXU_IDLE;
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initial state = `TXU_IDLE;
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// initial baud_counter = clocks_per_baud;
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// initial baud_counter = clocks_per_baud;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (i_reset)
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if (i_reset)
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begin
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begin
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baud_counter <= clocks_per_baud;
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baud_counter <= clocks_per_baud;
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o_uart <= 1'b1;
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o_uart <= 1'b1;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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state <= `TXU_IDLE;
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state <= `TXU_IDLE;
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lcl_data <= 8'h0;
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lcl_data <= 8'h0;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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end else if (i_break)
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end else if (i_break)
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begin
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begin
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baud_counter <= break_condition;
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baud_counter <= break_condition;
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o_uart <= 1'b0;
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o_uart <= 1'b0;
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state <= `TXU_BREAK;
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state <= `TXU_BREAK;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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end else if (baud_counter != 0)
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end else if (baud_counter != 0)
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begin // o_busy needs to be set coming into here
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begin // r_busy needs to be set coming into here
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baud_counter <= baud_counter - 28'h01;
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baud_counter <= baud_counter - 28'h01;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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end else if (state == `TXU_BREAK)
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end else if (state == `TXU_BREAK)
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begin
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begin
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state <= `TXU_IDLE;
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state <= `TXU_IDLE;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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o_uart <= 1'b1;
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o_uart <= 1'b1;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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// Give us two stop bits before becoming available
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// Give us two stop bits before becoming available
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baud_counter <= clocks_per_baud<<2;
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baud_counter <= clocks_per_baud<<2;
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end else if (state == `TXU_IDLE) // STATE_IDLE
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end else if (state == `TXU_IDLE) // STATE_IDLE
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begin
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begin
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// baud_counter <= 0;
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// baud_counter <= 0;
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r_setup <= i_setup;
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r_setup <= i_setup;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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if ((i_wr)&&(~o_busy))
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if ((i_wr)&&(~r_busy))
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begin // Immediately start us off with a start bit
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begin // Immediately start us off with a start bit
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o_uart <= 1'b0;
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o_uart <= 1'b0;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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case(data_bits)
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case(data_bits)
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2'b00: state <= `TXU_BIT_ZERO;
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2'b00: state <= `TXU_BIT_ZERO;
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2'b01: state <= `TXU_BIT_ONE;
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2'b01: state <= `TXU_BIT_ONE;
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2'b10: state <= `TXU_BIT_TWO;
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2'b10: state <= `TXU_BIT_TWO;
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2'b11: state <= `TXU_BIT_THREE;
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2'b11: state <= `TXU_BIT_THREE;
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endcase
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endcase
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lcl_data <= i_data;
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lcl_data <= i_data;
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baud_counter <= clocks_per_baud-28'h01;
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baud_counter <= clocks_per_baud-28'h01;
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end else begin // Stay in idle
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end else begin // Stay in idle
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o_uart <= 1'b1;
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o_uart <= 1'b1;
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o_busy <= 0;
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r_busy <= 0;
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// lcl_data is irrelevant
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// lcl_data is irrelevant
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// state <= state;
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// state <= state;
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end
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end
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end else begin
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end else begin
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// One clock tick in each of these states ...
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// One clock tick in each of these states ...
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baud_counter <= clocks_per_baud - 28'h01;
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baud_counter <= clocks_per_baud - 28'h01;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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if (state[3] == 0) // First 8 bits
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if (state[3] == 0) // First 8 bits
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begin
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begin
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o_uart <= lcl_data[0];
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o_uart <= lcl_data[0];
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calc_parity <= calc_parity ^ lcl_data[0];
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calc_parity <= calc_parity ^ lcl_data[0];
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if (state == `TXU_BIT_SEVEN)
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if (state == `TXU_BIT_SEVEN)
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state <= (use_parity)?`TXU_PARITY:`TXU_STOP;
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state <= (use_parity)?`TXU_PARITY:`TXU_STOP;
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else
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else
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state <= state + 1;
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state <= state + 1;
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lcl_data <= { 1'b0, lcl_data[7:1] };
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lcl_data <= { 1'b0, lcl_data[7:1] };
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end else if (state == `TXU_PARITY)
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end else if (state == `TXU_PARITY)
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begin
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begin
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state <= `TXU_STOP;
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state <= `TXU_STOP;
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if (fixd_parity)
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if (fixd_parity)
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o_uart <= parity_even;
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o_uart <= parity_even;
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else
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else
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o_uart <= calc_parity^((parity_even)? 1'b1:1'b0);
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o_uart <= calc_parity^((parity_even)? 1'b1:1'b0);
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end else if (state == `TXU_STOP)
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end else if (state == `TXU_STOP)
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begin // two stop bit(s)
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begin // two stop bit(s)
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o_uart <= 1'b1;
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o_uart <= 1'b1;
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if (dblstop)
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if (dblstop)
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state <= `TXU_SECOND_STOP;
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state <= `TXU_SECOND_STOP;
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else
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else
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state <= `TXU_IDLE;
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state <= `TXU_IDLE;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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end else // `TXU_SECOND_STOP and default:
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end else // `TXU_SECOND_STOP and default:
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begin
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begin
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state <= `TXU_IDLE; // Go back to idle
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state <= `TXU_IDLE; // Go back to idle
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o_uart <= 1'b1;
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o_uart <= 1'b1;
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// Still o_busy, since we need to wait
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// Still r_busy, since we need to wait
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// for the baud clock to finish counting
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// for the baud clock to finish counting
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// out this last bit.
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// out this last bit.
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end
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end
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end
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end
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end
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end
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// assign o_busy = (r_busy)||(~i_cts);
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assign o_busy = (r_busy);
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endmodule
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endmodule
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