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[/] [s6soc/] [trunk/] [rtl/] [wbpwmaudio.v] - Diff between revs 8 and 12

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Rev 8 Rev 12
Line 80... Line 80...
module  wbpwmaudio(i_clk,
module  wbpwmaudio(i_clk,
                // Wishbone interface
                // Wishbone interface
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                o_pwm, o_aux, o_int);
                o_pwm, o_aux, o_int);
        parameter       DEFAULT_RELOAD = 12'd1814, // about 44.1 kHz @  80MHz
        parameter       DEFAULT_RELOAD = 17'd1814, // about 44.1 kHz @  80MHz
                        //DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
                        //DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
                        NAUX=2, // Dev control values
                        NAUX=2, // Dev control values
                        VARIABLE_RATE=0,
                        VARIABLE_RATE=0,
                        TIMING_BITS=12;
                        TIMING_BITS=17;
        input   i_clk;
        input   i_clk;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input           i_wb_addr;
        input           i_wb_addr;
        input   [31:0]   i_wb_data;
        input   [31:0]   i_wb_data;
        output  reg             o_wb_ack;
        output  reg             o_wb_ack;
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        output  reg             o_int;
        output  reg             o_int;
 
 
 
 
        // How often shall we create an interrupt?  Every reload_value clocks!
        // How often shall we create an interrupt?  Every reload_value clocks!
        // If VARIABLE_RATE==0, this value will never change and will be kept
        // If VARIABLE_RATE==0, this value will never change and will be kept
        // at the default reload rate (44.1 kHz, for a 100 MHz clock)
        // at the default reload rate (defined up top)
        wire    [(TIMING_BITS-1):0]      w_reload_value;
        wire    [(TIMING_BITS-1):0]      w_reload_value;
        generate
        generate
        if (VARIABLE_RATE != 0)
        if (VARIABLE_RATE != 0)
        begin
        begin
                reg     [(TIMING_BITS-1):0]      r_reload_value;
                reg     [(TIMING_BITS-1):0]      r_reload_value;
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                o_int <= (~next_valid);
                o_int <= (~next_valid);
 
 
        reg     [15:0]   pwm_counter;
        reg     [15:0]   pwm_counter;
        initial pwm_counter = 16'h00;
        initial pwm_counter = 16'h00;
        always @(posedge i_clk)
        always @(posedge i_clk)
                pwm_counter <= pwm_counter + 1;
                pwm_counter <= pwm_counter + 16'h01;
 
 
        wire    [15:0]   br_counter;
        wire    [15:0]   br_counter;
        genvar  k;
        genvar  k;
        generate for(k=0; k<16; k=k+1)
        generate for(k=0; k<16; k=k+1)
        begin : bit_reversal_loop
        begin : bit_reversal_loop

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