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[/] [s6soc/] [trunk/] [rtl/] [wbpwmaudio.v] - Diff between revs 12 and 46

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Rev 12 Rev 46
Line 80... Line 80...
module  wbpwmaudio(i_clk,
module  wbpwmaudio(i_clk,
                // Wishbone interface
                // Wishbone interface
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                o_pwm, o_aux, o_int);
                o_pwm, o_aux, o_int);
        parameter       DEFAULT_RELOAD = 17'd1814, // about 44.1 kHz @  80MHz
        parameter       DEFAULT_RELOAD = 16'd1814, // about 44.1 kHz @  80MHz
                        //DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
                        //DEFAULT_RELOAD = 16'd2268,//about 44.1 kHz @ 100MHz
                        NAUX=2, // Dev control values
                        NAUX=2, // Dev control values
                        VARIABLE_RATE=0,
                        VARIABLE_RATE=0,
                        TIMING_BITS=17;
                        TIMING_BITS=16;
 
        localparam [0:0]  BITREVERSE=1;
        input   i_clk;
        input   i_clk;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input           i_wb_addr;
        input           i_wb_addr;
        input   [31:0]   i_wb_data;
        input   [31:0]   i_wb_data;
        output  reg             o_wb_ack;
        output  reg             o_wb_ack;
Line 107... Line 108...
        if (VARIABLE_RATE != 0)
        if (VARIABLE_RATE != 0)
        begin
        begin
                reg     [(TIMING_BITS-1):0]      r_reload_value;
                reg     [(TIMING_BITS-1):0]      r_reload_value;
                initial r_reload_value = DEFAULT_RELOAD;
                initial r_reload_value = DEFAULT_RELOAD;
                always @(posedge i_clk) // Data write
                always @(posedge i_clk) // Data write
                        if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
                        if ((i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
                                r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
                                r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
                assign  w_reload_value = r_reload_value;
                assign  w_reload_value = r_reload_value;
        end else begin
        end else begin
                assign  w_reload_value = DEFAULT_RELOAD;
                assign  w_reload_value = DEFAULT_RELOAD;
        end endgenerate
        end endgenerate
 
 
 
        reg                             ztimer;
        reg     [(TIMING_BITS-1):0]      timer;
        reg     [(TIMING_BITS-1):0]      timer;
        initial timer = DEFAULT_RELOAD;
        initial timer = DEFAULT_RELOAD;
 
        initial ztimer= 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (timer == 0)
                ztimer <= (timer == { {(TIMING_BITS-1){1'b0}}, 1'b1 });
 
        always @(posedge i_clk)
 
                if (ztimer)
                        timer <= w_reload_value;
                        timer <= w_reload_value;
                else
                else
                        timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
                        timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
 
 
        reg     [15:0]   sample_out;
        reg     [15:0]   sample_out;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (timer == 0)
                if (ztimer)
                        sample_out <= next_sample;
                        sample_out <= next_sample;
 
 
 
 
        reg     [15:0]   next_sample;
        reg     [15:0]   next_sample;
        reg             next_valid;
        reg             next_valid;
        initial next_valid = 1'b1;
        initial next_valid = 1'b1;
        initial next_sample = 16'h8000;
        initial next_sample = 16'h8000;
        always @(posedge i_clk) // Data write
        always @(posedge i_clk) // Data write
                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)
                if ((i_wb_stb)&&(i_wb_we)
                                &&((~i_wb_addr)||(VARIABLE_RATE==0)))
                                &&((~i_wb_addr)||(VARIABLE_RATE==0)))
                begin
                begin
                        // Write with two's complement data, convert it
                        // Write with two's complement data, convert it
                        // internally to binary offset
                        // internally to binary offset
                        next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
                        next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
                        next_valid <= 1'b1;
                        next_valid <= 1'b1;
                        if (i_wb_data[16])
                        if (i_wb_data[16])
                                o_aux <= i_wb_data[(NAUX+20-1):20];
                                o_aux <= i_wb_data[(NAUX+20-1):20];
                end else if (timer == 0)
                end else if (ztimer)
                        next_valid <= 1'b0;
                        next_valid <= 1'b0;
 
 
        initial o_int = 1'b0;
        initial o_int = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_int <= (~next_valid);
                o_int <= (~next_valid);
Line 158... Line 163...
 
 
        wire    [15:0]   br_counter;
        wire    [15:0]   br_counter;
        genvar  k;
        genvar  k;
        generate for(k=0; k<16; k=k+1)
        generate for(k=0; k<16; k=k+1)
        begin : bit_reversal_loop
        begin : bit_reversal_loop
                assign br_counter[k] = pwm_counter[15-k];
                assign br_counter[k] = (BITREVERSE)?pwm_counter[15-k]:pwm_counter[k];
        end endgenerate
        end endgenerate
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_pwm <= (sample_out >= br_counter);
                o_pwm <= (sample_out >= br_counter);
 
 
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                assign  o_wb_data = r_wb_data;
                assign  o_wb_data = r_wb_data;
        end endgenerate
        end endgenerate
 
 
        initial o_wb_ack = 1'b0;
        initial o_wb_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
                o_wb_ack <= (i_wb_stb);
        assign  o_wb_stall = 1'b0;
        assign  o_wb_stall = 1'b0;
 
 
endmodule
endmodule
 
 
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