OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [wbscope.v] - Diff between revs 46 and 51

Show entire file | Details | Blame | View Log

Rev 46 Rev 51
Line 9... Line 9...
//      The general operation is such that this 'scope' can record and report
//      The general operation is such that this 'scope' can record and report
//      on any 32 bit value transiting through the FPGA.  Once started and
//      on any 32 bit value transiting through the FPGA.  Once started and
//      reset, the scope records a copy of the input data every time the clock
//      reset, the scope records a copy of the input data every time the clock
//      ticks with the circuit enabled.  That is, it records these values up
//      ticks with the circuit enabled.  That is, it records these values up
//      until the trigger.  Once the trigger goes high, the scope will record
//      until the trigger.  Once the trigger goes high, the scope will record
//      for bw_holdoff more counts before stopping.  Values may then be read
//      for br_holdoff more counts before stopping.  Values may then be read
//      from the buffer, oldest to most recent.  After reading, the scope may
//      from the buffer, oldest to most recent.  After reading, the scope may
//      then be reset for another run.
//      then be reset for another run.
//
//
//      In general, therefore, operation happens in this fashion:
//      In general, therefore, operation happens in this fashion:
//              1. A reset is issued.
//              1. A reset is issued.
Line 85... Line 85...
//
//
module wbscope(i_clk, i_ce, i_trigger, i_data,
module wbscope(i_clk, i_ce, i_trigger, i_data,
        i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
        i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
        o_wb_ack, o_wb_stall, o_wb_data,
        o_wb_ack, o_wb_stall, o_wb_data,
        o_interrupt);
        o_interrupt);
        parameter       LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1,
        parameter [4:0]                  LGMEM = 5'd10;
                        DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4),
        parameter                       BUSW = 32;
                        HOLDOFFBITS = 20;
        parameter [0:0]                   SYNCHRONOUS=1;
 
        parameter                       HOLDOFFBITS = 20;
 
        parameter [(HOLDOFFBITS-1):0]    DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4);
        // The input signals that we wish to record
        // The input signals that we wish to record
        input                           i_clk, i_ce, i_trigger;
        input                           i_clk, i_ce, i_trigger;
        input           [(BUSW-1):0]     i_data;
        input           [(BUSW-1):0]     i_data;
        // The WISHBONE bus for reading and configuring this scope
        // The WISHBONE bus for reading and configuring this scope
        input                           i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
        input                           i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
Line 108... Line 110...
        reg     [(BUSW-1):0]     mem[0:((1<<LGMEM)-1)];
        reg     [(BUSW-1):0]     mem[0:((1<<LGMEM)-1)];
 
 
        // Our status/config register
        // Our status/config register
        wire            bw_reset_request, bw_manual_trigger,
        wire            bw_reset_request, bw_manual_trigger,
                        bw_disable_trigger, bw_reset_complete;
                        bw_disable_trigger, bw_reset_complete;
        reg     [22:0]   br_config;
        reg     [2:0]    br_config;
        wire    [(HOLDOFFBITS-1):0]      bw_holdoff;
        reg     [(HOLDOFFBITS-1):0]      br_holdoff;
        initial br_config = DEFAULT_HOLDOFF;
        initial br_config = 3'b0;
 
        initial br_holdoff = DEFAULT_HOLDOFF;
        always @(posedge i_wb_clk)
        always @(posedge i_wb_clk)
                if ((i_wb_stb)&&(~i_wb_addr))
                if ((i_wb_stb)&&(!i_wb_addr))
                begin
                begin
                        if (i_wb_we)
                        if (i_wb_we)
 
                        begin
                                br_config <= { i_wb_data[31],
                                br_config <= { i_wb_data[31],
                                        (i_wb_data[27]),
                                        i_wb_data[27],
                                        i_wb_data[26],
                                        i_wb_data[26] };
                                        i_wb_data[19:0] };
                                br_holdoff = i_wb_data[(HOLDOFFBITS-1):0];
 
                        end
                end else if (bw_reset_complete)
                end else if (bw_reset_complete)
                        br_config[22] <= 1'b1;
                        br_config[2] <= 1'b1;
        assign  bw_reset_request   = (~br_config[22]);
        assign  bw_reset_request   = (!br_config[2]);
        assign  bw_manual_trigger  = (br_config[21]);
        assign  bw_manual_trigger  = (br_config[1]);
        assign  bw_disable_trigger = (br_config[20]);
        assign  bw_disable_trigger = (br_config[0]);
        assign  bw_holdoff         = br_config[(HOLDOFFBITS-1):0];
 
 
 
        wire    dw_reset, dw_manual_trigger, dw_disable_trigger;
        wire    dw_reset, dw_manual_trigger, dw_disable_trigger;
        generate
        generate
        if (SYNCHRONOUS > 0)
        if (SYNCHRONOUS > 0)
        begin
        begin
Line 178... Line 182...
        // Write with the i-clk, or input clock.  All outputs read with the
        // Write with the i-clk, or input clock.  All outputs read with the
        // WISHBONE-clk, or i_wb_clk clock.
        // WISHBONE-clk, or i_wb_clk clock.
        reg     dr_triggered, dr_primed;
        reg     dr_triggered, dr_primed;
        wire    dw_trigger;
        wire    dw_trigger;
        assign  dw_trigger = (dr_primed)&&(
        assign  dw_trigger = (dr_primed)&&(
                                ((i_trigger)&&(~dw_disable_trigger))
                                ((i_trigger)&&(!dw_disable_trigger))
                                ||(dr_triggered)
 
                                ||(dw_manual_trigger));
                                ||(dw_manual_trigger));
        initial dr_triggered = 1'b0;
        initial dr_triggered = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (dw_reset)
                if (dw_reset)
                        dr_triggered <= 1'b0;
                        dr_triggered <= 1'b0;
Line 194... Line 197...
        // Determine when memory is full and capture is complete
        // Determine when memory is full and capture is complete
        //
        //
        // Writes take place on the data clock
        // Writes take place on the data clock
        // The counter is unsigned
        // The counter is unsigned
        (* ASYNC_REG="TRUE" *) reg      [(HOLDOFFBITS-1):0]      counter;
        (* ASYNC_REG="TRUE" *) reg      [(HOLDOFFBITS-1):0]      counter;
        reg     less_than_holdoff;
 
        always @(posedge i_clk)
 
                if (dw_reset)
 
                        less_than_holdoff <= 1'b1;
 
                else if (i_ce)
 
                        less_than_holdoff <= (counter < bw_holdoff);
 
 
 
        reg             dr_stopped;
        reg             dr_stopped;
        initial dr_stopped = 1'b0;
        initial dr_stopped = 1'b0;
        initial counter = 0;
        initial counter = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (dw_reset)
                if (dw_reset)
                        counter <= 0;
                        counter <= 0;
                else if ((i_ce)&&(dr_triggered)&&(~dr_stopped))
                else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
                begin // MUST BE a < and not <=, so that we can keep this w/in
                begin // MUST BE a < and not <=, so that we can keep this w/in
                        // 20 bits.  Else we'd need to add a bit to comparison 
                        // 20 bits.  Else we'd need to add a bit to comparison 
                        // here.
                        // here.
                        counter <= counter + 1'b1;
                        counter <= counter + 1'b1;
                end
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((~dr_triggered)||(dw_reset))
                if ((!dr_triggered)||(dw_reset))
                        dr_stopped <= 1'b0;
                        dr_stopped <= 1'b0;
                else if (i_ce)
 
                        dr_stopped <= (counter+1'b1 >= bw_holdoff);
 
                else
                else
                        dr_stopped <= (counter >= bw_holdoff);
                        dr_stopped <= (counter >= br_holdoff);
 
 
        //
        //
        //      Actually do our writes to memory.  Record, via 'primed' when
        //      Actually do our writes to memory.  Record, via 'primed' when
        //      the memory is full.
        //      the memory is full.
        //
        //
Line 294... Line 289...
        always @(posedge i_wb_clk)
        always @(posedge i_wb_clk)
        begin
        begin
                if ((bw_reset_request)
                if ((bw_reset_request)
                        ||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
                        ||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
                        raddr <= 0;
                        raddr <= 0;
                else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped))
                else if ((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)&&(bw_stopped))
                        raddr <= raddr + 1'b1; // Data read, when stopped
                        raddr <= raddr + 1'b1; // Data read, when stopped
 
 
                if ((bw_cyc_stb)&&(~i_wb_we))
                if ((bw_cyc_stb)&&(!i_wb_we))
                begin // Read from the bus
                begin // Read from the bus
                        br_wb_ack <= 1'b1;
                        br_wb_ack <= 1'b1;
                end else if ((bw_cyc_stb)&&(i_wb_we))
                end else if ((bw_cyc_stb)&&(i_wb_we))
                        // We did this write above
                        // We did this write above
                        br_wb_ack <= 1'b1;
                        br_wb_ack <= 1'b1;
Line 310... Line 305...
        end
        end
 
 
        reg     [31:0]   nxt_mem;
        reg     [31:0]   nxt_mem;
        always @(posedge i_wb_clk)
        always @(posedge i_wb_clk)
                nxt_mem <= mem[raddr+waddr+
                nxt_mem <= mem[raddr+waddr+
                        (((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)) ?
                        (((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)) ?
                                {{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
                                {{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
 
 
        wire    [19:0]   full_holdoff;
        wire    [19:0]   full_holdoff;
        assign full_holdoff[(HOLDOFFBITS-1):0] = bw_holdoff;
        assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
        generate if (HOLDOFFBITS < 20)
        generate if (HOLDOFFBITS < 20)
                assign full_holdoff[19:(HOLDOFFBITS)] = 0;
                assign full_holdoff[19:(HOLDOFFBITS)] = 0;
        endgenerate
        endgenerate
 
 
        wire    [4:0]    bw_lgmem;
        wire    [4:0]    bw_lgmem;
        assign          bw_lgmem = LGMEM;
        assign          bw_lgmem = LGMEM;
        always @(posedge i_wb_clk)
        always @(posedge i_wb_clk)
                if (~i_wb_addr) // Control register read
                if (!i_wb_addr) // Control register read
                        o_wb_data <= { bw_reset_request,
                        o_wb_data <= { bw_reset_request,
                                        bw_stopped,
                                        bw_stopped,
                                        bw_triggered,
                                        bw_triggered,
                                        bw_primed,
                                        bw_primed,
                                        bw_manual_trigger,
                                        bw_manual_trigger,
                                        bw_disable_trigger,
                                        bw_disable_trigger,
                                        (raddr == {(LGMEM){1'b0}}),
                                        (raddr == {(LGMEM){1'b0}}),
                                        bw_lgmem,
                                        bw_lgmem,
                                        full_holdoff  };
                                        full_holdoff  };
                else if (~bw_stopped) // read, prior to stopping
                else if (!bw_stopped) // read, prior to stopping
                        o_wb_data <= i_data;
                        o_wb_data <= i_data;
                else // if (i_wb_addr) // Read from FIFO memory
                else // if (i_wb_addr) // Read from FIFO memory
                        o_wb_data <= nxt_mem; // mem[raddr+waddr];
                        o_wb_data <= nxt_mem; // mem[raddr+waddr];
 
 
        assign  o_wb_stall = 1'b0;
        assign  o_wb_stall = 1'b0;
        assign  o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
        assign  o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
 
 
        reg     br_level_interrupt;
        reg     br_level_interrupt;
        initial br_level_interrupt = 1'b0;
        initial br_level_interrupt = 1'b0;
        assign  o_interrupt = (bw_stopped)&&(~bw_disable_trigger)
        assign  o_interrupt = (bw_stopped)&&(!bw_disable_trigger)
                                        &&(~br_level_interrupt);
                                        &&(!br_level_interrupt);
        always @(posedge i_wb_clk)
        always @(posedge i_wb_clk)
                if ((bw_reset_complete)||(bw_reset_request))
                if ((bw_reset_complete)||(bw_reset_request))
                        br_level_interrupt<= 1'b0;
                        br_level_interrupt<= 1'b0;
                else
                else
                        br_level_interrupt<= (bw_stopped)&&(~bw_disable_trigger);
                        br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger);
 
 
endmodule
endmodule
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.