| Line 9... |
Line 9... |
// The general operation is such that this 'scope' can record and report
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// The general operation is such that this 'scope' can record and report
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// on any 32 bit value transiting through the FPGA. Once started and
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// on any 32 bit value transiting through the FPGA. Once started and
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// reset, the scope records a copy of the input data every time the clock
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// reset, the scope records a copy of the input data every time the clock
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// ticks with the circuit enabled. That is, it records these values up
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// ticks with the circuit enabled. That is, it records these values up
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// until the trigger. Once the trigger goes high, the scope will record
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// until the trigger. Once the trigger goes high, the scope will record
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// for bw_holdoff more counts before stopping. Values may then be read
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// for br_holdoff more counts before stopping. Values may then be read
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// from the buffer, oldest to most recent. After reading, the scope may
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// from the buffer, oldest to most recent. After reading, the scope may
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// then be reset for another run.
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// then be reset for another run.
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//
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//
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// In general, therefore, operation happens in this fashion:
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// In general, therefore, operation happens in this fashion:
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// 1. A reset is issued.
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// 1. A reset is issued.
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| Line 85... |
Line 85... |
//
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//
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module wbscope(i_clk, i_ce, i_trigger, i_data,
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module wbscope(i_clk, i_ce, i_trigger, i_data,
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i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_interrupt);
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o_interrupt);
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parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1,
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parameter [4:0] LGMEM = 5'd10;
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DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4),
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parameter BUSW = 32;
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HOLDOFFBITS = 20;
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parameter [0:0] SYNCHRONOUS=1;
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parameter HOLDOFFBITS = 20;
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parameter [(HOLDOFFBITS-1):0] DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4);
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// The input signals that we wish to record
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// The input signals that we wish to record
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input i_clk, i_ce, i_trigger;
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input i_clk, i_ce, i_trigger;
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input [(BUSW-1):0] i_data;
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input [(BUSW-1):0] i_data;
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// The WISHBONE bus for reading and configuring this scope
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// The WISHBONE bus for reading and configuring this scope
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input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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| Line 108... |
Line 110... |
reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
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reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
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|
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// Our status/config register
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// Our status/config register
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wire bw_reset_request, bw_manual_trigger,
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wire bw_reset_request, bw_manual_trigger,
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bw_disable_trigger, bw_reset_complete;
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bw_disable_trigger, bw_reset_complete;
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reg [22:0] br_config;
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reg [2:0] br_config;
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wire [(HOLDOFFBITS-1):0] bw_holdoff;
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reg [(HOLDOFFBITS-1):0] br_holdoff;
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initial br_config = DEFAULT_HOLDOFF;
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initial br_config = 3'b0;
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initial br_holdoff = DEFAULT_HOLDOFF;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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if ((i_wb_stb)&&(~i_wb_addr))
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if ((i_wb_stb)&&(!i_wb_addr))
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begin
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begin
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if (i_wb_we)
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if (i_wb_we)
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begin
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br_config <= { i_wb_data[31],
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br_config <= { i_wb_data[31],
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(i_wb_data[27]),
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i_wb_data[27],
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i_wb_data[26],
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i_wb_data[26] };
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i_wb_data[19:0] };
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br_holdoff = i_wb_data[(HOLDOFFBITS-1):0];
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end
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end else if (bw_reset_complete)
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end else if (bw_reset_complete)
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br_config[22] <= 1'b1;
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br_config[2] <= 1'b1;
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assign bw_reset_request = (~br_config[22]);
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assign bw_reset_request = (!br_config[2]);
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assign bw_manual_trigger = (br_config[21]);
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assign bw_manual_trigger = (br_config[1]);
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assign bw_disable_trigger = (br_config[20]);
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assign bw_disable_trigger = (br_config[0]);
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assign bw_holdoff = br_config[(HOLDOFFBITS-1):0];
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|
|
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wire dw_reset, dw_manual_trigger, dw_disable_trigger;
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wire dw_reset, dw_manual_trigger, dw_disable_trigger;
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generate
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generate
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if (SYNCHRONOUS > 0)
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if (SYNCHRONOUS > 0)
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begin
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begin
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| Line 178... |
Line 182... |
// Write with the i-clk, or input clock. All outputs read with the
|
// Write with the i-clk, or input clock. All outputs read with the
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// WISHBONE-clk, or i_wb_clk clock.
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// WISHBONE-clk, or i_wb_clk clock.
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reg dr_triggered, dr_primed;
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reg dr_triggered, dr_primed;
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wire dw_trigger;
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wire dw_trigger;
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assign dw_trigger = (dr_primed)&&(
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assign dw_trigger = (dr_primed)&&(
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((i_trigger)&&(~dw_disable_trigger))
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((i_trigger)&&(!dw_disable_trigger))
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||(dr_triggered)
|
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||(dw_manual_trigger));
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||(dw_manual_trigger));
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initial dr_triggered = 1'b0;
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initial dr_triggered = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (dw_reset)
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if (dw_reset)
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dr_triggered <= 1'b0;
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dr_triggered <= 1'b0;
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| Line 194... |
Line 197... |
// Determine when memory is full and capture is complete
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// Determine when memory is full and capture is complete
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//
|
//
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// Writes take place on the data clock
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// Writes take place on the data clock
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// The counter is unsigned
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// The counter is unsigned
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(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] counter;
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(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] counter;
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reg less_than_holdoff;
|
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always @(posedge i_clk)
|
|
if (dw_reset)
|
|
less_than_holdoff <= 1'b1;
|
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else if (i_ce)
|
|
less_than_holdoff <= (counter < bw_holdoff);
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|
|
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reg dr_stopped;
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reg dr_stopped;
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initial dr_stopped = 1'b0;
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initial dr_stopped = 1'b0;
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initial counter = 0;
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initial counter = 0;
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always @(posedge i_clk)
|
always @(posedge i_clk)
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if (dw_reset)
|
if (dw_reset)
|
counter <= 0;
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counter <= 0;
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else if ((i_ce)&&(dr_triggered)&&(~dr_stopped))
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else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
|
begin // MUST BE a < and not <=, so that we can keep this w/in
|
begin // MUST BE a < and not <=, so that we can keep this w/in
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// 20 bits. Else we'd need to add a bit to comparison
|
// 20 bits. Else we'd need to add a bit to comparison
|
// here.
|
// here.
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counter <= counter + 1'b1;
|
counter <= counter + 1'b1;
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end
|
end
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always @(posedge i_clk)
|
always @(posedge i_clk)
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if ((~dr_triggered)||(dw_reset))
|
if ((!dr_triggered)||(dw_reset))
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dr_stopped <= 1'b0;
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dr_stopped <= 1'b0;
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else if (i_ce)
|
|
dr_stopped <= (counter+1'b1 >= bw_holdoff);
|
|
else
|
else
|
dr_stopped <= (counter >= bw_holdoff);
|
dr_stopped <= (counter >= br_holdoff);
|
|
|
//
|
//
|
// Actually do our writes to memory. Record, via 'primed' when
|
// Actually do our writes to memory. Record, via 'primed' when
|
// the memory is full.
|
// the memory is full.
|
//
|
//
|
| Line 294... |
Line 289... |
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
begin
|
begin
|
if ((bw_reset_request)
|
if ((bw_reset_request)
|
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
|
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
|
raddr <= 0;
|
raddr <= 0;
|
else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped))
|
else if ((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)&&(bw_stopped))
|
raddr <= raddr + 1'b1; // Data read, when stopped
|
raddr <= raddr + 1'b1; // Data read, when stopped
|
|
|
if ((bw_cyc_stb)&&(~i_wb_we))
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if ((bw_cyc_stb)&&(!i_wb_we))
|
begin // Read from the bus
|
begin // Read from the bus
|
br_wb_ack <= 1'b1;
|
br_wb_ack <= 1'b1;
|
end else if ((bw_cyc_stb)&&(i_wb_we))
|
end else if ((bw_cyc_stb)&&(i_wb_we))
|
// We did this write above
|
// We did this write above
|
br_wb_ack <= 1'b1;
|
br_wb_ack <= 1'b1;
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| Line 310... |
Line 305... |
end
|
end
|
|
|
reg [31:0] nxt_mem;
|
reg [31:0] nxt_mem;
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
nxt_mem <= mem[raddr+waddr+
|
nxt_mem <= mem[raddr+waddr+
|
(((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)) ?
|
(((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)) ?
|
{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
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{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
|
|
|
wire [19:0] full_holdoff;
|
wire [19:0] full_holdoff;
|
assign full_holdoff[(HOLDOFFBITS-1):0] = bw_holdoff;
|
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
|
generate if (HOLDOFFBITS < 20)
|
generate if (HOLDOFFBITS < 20)
|
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
|
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
|
endgenerate
|
endgenerate
|
|
|
wire [4:0] bw_lgmem;
|
wire [4:0] bw_lgmem;
|
assign bw_lgmem = LGMEM;
|
assign bw_lgmem = LGMEM;
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
if (~i_wb_addr) // Control register read
|
if (!i_wb_addr) // Control register read
|
o_wb_data <= { bw_reset_request,
|
o_wb_data <= { bw_reset_request,
|
bw_stopped,
|
bw_stopped,
|
bw_triggered,
|
bw_triggered,
|
bw_primed,
|
bw_primed,
|
bw_manual_trigger,
|
bw_manual_trigger,
|
bw_disable_trigger,
|
bw_disable_trigger,
|
(raddr == {(LGMEM){1'b0}}),
|
(raddr == {(LGMEM){1'b0}}),
|
bw_lgmem,
|
bw_lgmem,
|
full_holdoff };
|
full_holdoff };
|
else if (~bw_stopped) // read, prior to stopping
|
else if (!bw_stopped) // read, prior to stopping
|
o_wb_data <= i_data;
|
o_wb_data <= i_data;
|
else // if (i_wb_addr) // Read from FIFO memory
|
else // if (i_wb_addr) // Read from FIFO memory
|
o_wb_data <= nxt_mem; // mem[raddr+waddr];
|
o_wb_data <= nxt_mem; // mem[raddr+waddr];
|
|
|
assign o_wb_stall = 1'b0;
|
assign o_wb_stall = 1'b0;
|
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
|
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
|
|
|
reg br_level_interrupt;
|
reg br_level_interrupt;
|
initial br_level_interrupt = 1'b0;
|
initial br_level_interrupt = 1'b0;
|
assign o_interrupt = (bw_stopped)&&(~bw_disable_trigger)
|
assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger)
|
&&(~br_level_interrupt);
|
&&(!br_level_interrupt);
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
if ((bw_reset_complete)||(bw_reset_request))
|
if ((bw_reset_complete)||(bw_reset_request))
|
br_level_interrupt<= 1'b0;
|
br_level_interrupt<= 1'b0;
|
else
|
else
|
br_level_interrupt<= (bw_stopped)&&(~bw_disable_trigger);
|
br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger);
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
