OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [sw/] [host/] [regdefs.h] - Diff between revs 11 and 12

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 11 Rev 12
Line 112... Line 112...
#define RESET_ADDRESS   0x00480000 // ZipCPU Reset address
#define RESET_ADDRESS   0x00480000 // ZipCPU Reset address
 
 
// Interrupt control constants
// Interrupt control constants
#define GIE             0x80000000      // Enable all interrupts
#define GIE             0x80000000      // Enable all interrupts
#define SCOPEN          0x80040004      // Enable WBSCOPE interrupts
#define SCOPEN          0x80040004      // Enable WBSCOPE interrupts
#define ISPIF_EN        0x90001000      // Enable SPI Flash interrupts
#define ISPIF_EN        0x88000800      // Enable SPI Flash interrupts
#define ISPIF_DIS       0x10000000      // Disable SPI Flash interrupts
#define ISPIF_DIS       0x08000000      // Disable SPI Flash interrupts
#define ISPIF_CLR       0x10001000      // Clear pending SPI Flash interrupt
#define ISPIF_CLR       0x08000800      // Clear pending SPI Flash interrupt
 
 
// Flash control constants
// Flash control constants
#define ERASEFLAG       0x80000000
#define ERASEFLAG       0x80000000
#define DISABLEWP       0x10000000
#define DISABLEWP       0x10000000
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.