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} WBSCOPE;
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} WBSCOPE;
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#define IOADDR 0x000400
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#define IOADDR 0x000400
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#define SCOPEADDR 0x000800
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#define SCOPEADDR 0x000800
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// #define FCTLADDR 0x000c00 // Flash control, depends upon write capability
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// #define FCTLADDR 0x000c00 // Flash control, depends upon write capability
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#define RAMADDR 0x004000
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#define BKRAM (void *)0x004000
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#define RAMSZ (RAMADDR)
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#define FLASH (void *)0x1000000
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#define FLASHADDR 0x1000000
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#define SDRAM (void *)0
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#define MEMLEN 0x04000
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#define FLASHLEN 0x1000000
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#define RESET_ADDR 0x1200000
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#define RESET_ADDR 0x1200000
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#define FLASHSZ (FLASHADDR)
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#define CLOCKFREQHZ 80000000
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#define CLOCKFREQ_HZ CLOCKFREQHZ
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static volatile IOSPACE *const _sys = (IOSPACE *)IOADDR;
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static volatile IOSPACE *const _sys = (IOSPACE *)IOADDR;
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#define _ZIP_HAS_WBUARTRX
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#define _uartrx _sys->io_uart
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#define _ZIP_HAS_LONELY_UART
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#define LONELY_UART
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#define _uart _sys->io_uart
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#define _ZIP_HAS_WATCHDOG
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#define _watchdog _sys->io_watchdog
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static volatile WBSCOPE *const _scope = (WBSCOPE *)SCOPEADDR;
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static volatile WBSCOPE *const _scope = (WBSCOPE *)SCOPEADDR;
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#define valid_ram_region(PTR,LN) (((int)(PTR)>=RAMADDR)&&((int)(PTR+LN)<RAMADDR+RAMSZ))
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#define valid_ram_region(PTR,LN) ((((char *)PTR)>=(char *)BKRAM)&&((((char *)PTR)+LN)<(char *)BKRAM+MEMLEN))
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#define valid_flash_region(PTR,LN) (((int)(PTR)>=FLASHADDR)&&((int)(PTR+LN)<FLASHADDR+FLASHSZ))
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#define valid_flash_region(PTR,LN) ((((char *)PTR)>=(char *)FLASH)&&((((char *)PTR)+LN)<(char *)FLASH+FLASHLEN))
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#define valid_mem_region(PTR,LN) ((valid_ram_region(PTR,LN))||(valid_flash_region(PTR,LN)))
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#define valid_mem_region(PTR,LN) ((valid_ram_region(PTR,LN))||(valid_flash_region(PTR,LN)))
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#endif
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#endif
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