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[/] [scan_based_serial_communication/] [trunk/] [SCAN_README.txt] - Diff between revs 3 and 4

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AUTHOR
AUTHOR
        David Fick - dfick@umich.edu
        David Fick - dfick@umich.edu
 
 
VERSION
VERSION
        1.0 - June 27, 2010
        1.0 - June 27, 2010
 
        1.1 - January 7, 2011
 
 
SCAN DESCRIPTION
SCAN DESCRIPTION
        This is a simple scan chain implemented with deperlify. It has been
        This is a simple scan chain implemented with deperlify. It has been
        used, successfully, on multiple tapeouts.
        used, successfully, on multiple tapeouts.
 
 
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        from the chip, first raise "scan_load_chain" high, pulse the two
        from the chip, first raise "scan_load_chain" high, pulse the two
        clocks once as normal, then lower "scan_load_chain". Now that
        clocks once as normal, then lower "scan_load_chain". Now that
        the chip data has been loaded into the scan chain, clock out the
        the chip data has been loaded into the scan chain, clock out the
        data as normal.
        data as normal.
 
 
        Due to the buffering latch, complex internal interfaces can be
        To create a large number of bits, address and data fields may
 
        be created for a signal. 2^addr_bits*data_bits must be greater
 
        than the size. In this way, only addr_bits+data_bits number of
 
        bits may be generated in the scan chain, which reduces the
 
        length of the scan chain, as well as the area, since latches
 
        are much smaller than the muxing elements needed for the
 
        chain. Since this is a new feature, the size specified by the
 
        address and data bits should most likely match the total size
 
        in order to avoid bugs.
 
 
 
        Due to the buffering latches, complex internal interfaces can be
        emulated using the scan chain. For instance, an SRAM could be
        emulated using the scan chain. For instance, an SRAM could be
        connected to a clock, chip select, write enable, 64-bit data-in,
        connected to a clock, chip select, write enable, 64-bit data-in,
        and 64-bit data-out, all of which are connected to the scan
        and 64-bit data-out, all of which are connected to the scan
        chain. The scan chain would need to be used a few times for each
        chain. The scan chain would need to be used a few times for each
        "cycle" of the SRAM. For instance, each time the clock signal
        "cycle" of the SRAM. For instance, each time the clock signal
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        The example description below has additional information about
        The example description below has additional information about
        how to use the scan chain.
        how to use the scan chain.
 
 
 
 
EXAMPLE DESCRIPTION
EXAMPLE DESCRIPTION
        To run the example, use deperlify to generate scan.v and
        To run the example, call "make". The example uses Synopsys VCS.
        scan_testbench.v:
 
 
 
        perl deperlify.pl scan.perl.v
 
        perl depeflify.pl scan_testbench.perl.v
 
 
 
        Then use your Verilog simulator of choice.
 
 
 
        This example takes advantage of the DEPERLIFY_INCLUDE command. The
        This example takes advantage of the DEPERLIFY_INCLUDE command. The
        scan.perl.v file reads in the data structure scan_signal_list.pl
        scan.perl.v file reads in the data structure scan_signal_list.pl
        in order to generate the scan chain. The file scan_testbench.perl.v
        in order to generate the scan chain. The file scan_testbench.perl.v
        uses the same data structure to generate variables and functions
        uses the same data structure to generate variables and functions

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